An energy efficient synthesis flow for application specific SoC design

Abstract

Multiple Supply Voltage (MSV) is a known design technique to deal with the power and thermal issues of Multi Processor System on Chips (MPSoCs). In this paper, an MSV driven synthesis flow is proposed in four phases for the design of application-specific MPSoCs. The first phase conducts the core-to-router allocation concerning the operating voltages of cores as well as the bandwidth/latency requirements of the data flowing between the cores. The second phase coordinates voltages of cores connected to the same router. The third phase refines the power delivery network using our proposed voltage-aware hierarchical floorplanning algorithm. Finally, router-to-router connection and path allocation are done by the use of existing methods in the last phase. For the first time, we perform the core to router allocation phase before the voltage islanding phase to find the highest number of design solutions satisfying the set of given constraints; this in turn, improves the flexibility and efficiency of our synthesis process. Exhaustive experimental evaluations have been done on real-world benchmarks. Results confirm achieving 90% more design solutions (to conduct a wiser design space exploration) and an average of 93% Energy Delay Product (EDP) improvement as compared to the existing synthesis approaches.