SoC Design Research Articles

Verification of Dual Port RAM using System Verilog and UVM

Verification process place a prominent role in the field of SoC and ASIC design. Several verification methodologies are there apart from those Universal Verification Methodology (UVM) is advanced and it is widely used by the industries due to its special features. UVM provides reusable and well-structured verification components by using System Verilog class library. In this work, Dual Port RAM is considered as Design Under Test (DUT). System Verilog and UVM verification environments are developed to verify the DUT. Assertion and cover group coverage are set up with a goal of achieving 100% from both the environments.

High Priority Arbitration for Less Burst Data Transactions for Improved Average Waiting Time of Multi-Processor Cores

The multi-processor cores in SoC which have high burst data transactions can play a critical role while accessing the shared resources such as the off-chip memory. These processor cores can starve other processor cores that have less burst data transactions while accessing the same shared resources. The starving issue of other processor cores leads to degrade the entire system performance of the SoC. However, the arbiter architecture in the SoC design plays the best solution to manage different processor core requests and granting one of them to access the shared resources according to different scheduling algorithms. In this paper, we have designed AXI interconnect, which includes arbiter architecture to connect four processor cores represented by the AXI masters and the off-chip memory represented by the salve. Each processor core (AXI Master) uses the AXI4 interface protocol to improve the system performance and the arbiter based on the static fixed-priority algorithm to improve the average waiting time for all the processor cores. The SoC design architecture is modeled in System Verilog HDL; simulation and synthesis are done by using the Vivado tool and FPGA ZYNQ-7 ZC702 Evaluation Board (xc7z020clg484-1).

SEMIFIVE and Arm Accelerate Custom SoC Designs

SEMIFIVE and Arm Accelerate Custom SoC Designs

An Adaptive Fault-Tolerant and Congestion Controlled Selection Strategy for Networks on Chip

Background & Objective: Networks on chip are being developed as a communication infrastructure in the design of multiprocessor SOCs. With the reduction in feature size, transient faults on the links are becoming a major issue on the performance of NOCs. Methods: In this paper, two fault-tolerant algorithms are proposed. In the first algorithm, a faulty link tolerant algorithm is designed which by measuring network loads on the links will reduce transient faults and balances the load. To address the effect of hardware faults, fault and congestion controlled algorithm is designed that not only control the congestion, but also the faults on both links and the nodes. Results: The packet size is taken as 8 flits and data width of 32 bits are considered for all switches. Input buffers are having 8 slots for storing data. The simulations are carried over two synthetic traffic scenarios that are, hotspot and transpose. Conclusion: The proposed strategies are evaluated on two different synthetic traffic patterns and the results so obtained shows better network and hardware performance of both the routing in comparison with non-fault-tolerant routing.

Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL

The emergence of virtual prototypes (VPs) at the electronic system level (ESL) has played a major role in modernizing the system-on-chips (SoCs) design process to raise design productivity and reduce time-to-market. A VP is an abstract and executable software model implemented typically using SystemC and its transaction-level modeling (TLM) framework. However, this modern VP-based design process still has weaknesses, in particular, due to the significant manual effort involved for design understanding, analysis, and modeling tasks which is both time consuming and error-prone. This article introduces an automated and fast design understanding approach that enables designers to trace detailed information of the VPs’ structure and behavior. Experimental results including a real-world VP-based SoC show the advantages of our approach, such as its accuracy, applicability, and scalability.

Design of a BP neural network SoC based on domestic embedded CPU

Design of a BP neural network SoC based on domestic embedded CPU

Beyond Cache Attacks

System-on-Chips (SoCs) are a key enabling technology for the Internet-of-Things (IoT), a hyper-connected world where on- and inter-chip communication is ubiquitous. SoCs usually integrate cryptographic hardware cores for confidentiality and authentication services. However, these components are prone to implementation attacks. During the operation of a cryptographic core, the secret key may passively be inferred through cache observations. Access-driven attacks exploiting these observations are therefore a vital threat to SoCs operating in IoT environments. Previous works have shown the feasibility of these attacks in the SoC context. Yet, the SoC communication structure can be used to further improve access-based cache attacks. The communication attacks are not as well-understood as other micro-architectural attacks. It is important to raise the awareness of SoC designers of such a threat. To this end, we present four contributions. First, we demonstrate an improved Prime+Probe attack on four different AES-128 implementations (original transformation tables, T 0 -Only, T 2KB , and S-Box). As a novelty, this attack exploits the collisions of the bus-based SoC communication to further increase its efficiency. Second, we explore the impact of preloading on the efficiency of our communication-optimized attack. Third, we integrate three countermeasures ( shuffling , mini-tables , and Time-Division Multiple Access (TDMA) bus arbitration ) and evaluate their impact on the attack. Although shuffling and mini-tables countermeasures were proposed in previous work, their application as countermeasures against the bus-based attack was not studied before. In addition, TDMA as a countermeasure for bus-based attacks is an original contribution of this work. Fourth, we further discuss the implications of our work in the SoC design and its perspective with the new cryptographic primitives proposed in the ongoing National Institute of Standard and Technology Lightweight Cryptography competition. The results show that our improved communication-optimized attack is efficient, speeding up full key recovery by up to 400 times when compared to the traditional Prime+Probe technique. Moreover, the protection techniques are feasible and effectively mitigate the proposed improved attack.

Hardware Architecture Exploration for Deep Neural Networks

Owing to good performance, deep Convolution Neural Networks (CNNs) are rapidly rising in popularity across a broad range of applications. Since high accuracy CNNs are both computation intensive and memory intensive, many researchers have shown significant interest in the accelerator design. Furthermore, the AI chip market size grows and the competition on the performance, cost, and power consumption of the artificial intelligence SoC designs is increasing. Therefore, it is important to develop design techniques and platforms that are useful for the efficient design of optimized AI architectures to satisfy the given specifications in a short design time. In this research, we have developed design space exploration techniques and environments for the optimal design of the overall system including computing modules and memories. Our current design platform is built using NVIDIA Deep Learning Accelerator as a computing model, SRAM as a buffer, and DRAM with GDDR6 as an off-chip memory. We also developed a program to estimate the processing time of a given neural network. By modifying both the on-chip SRAM size and the computing module size, a designer can explore the design space efficiently, and then choose the optimal architecture which shows the minimal cost while satisfying the performance specification. To illustrate the operation of the design platform, two well-known deep CNNs are used, which are YOLOv3 and faster RCNN. This technology can be used to explore and to optimize the hardware architectures of the CNNs so that the cost can be minimized.

Hierarchical Methodology Approach to SOC Design: A Comprehensive Look

With the process node (CMOS transistor size) becoming increasingly smaller, there is an ever-increasing need for the software to handle the large gate count with faster turnaround time and better accuracy. Reaching timing closure on multi-million gate VLSI chips using flat flow is infeasible due to hardware capacity limit, and excessive run time overheads. New flows and design implementations need to be introduced to manage the scalability of design sizes by scaling down the memory usage and run time. Traditionally, the flat implementation of designs was used for smaller designs with maximum accuracy. Then the hierarchical approach was introduced to better the run time and handle the millions of gates by partitioning and assembling. Through this paper, we are going to look at the various implementation flows and its artifacts viz. flat, traditional hierarchical, models, post assembly ECO, context views, feasibility flows . We are also going to look at a advances in the technology of timing graph reduction and physical data reduction that enables new flow implementations and can be applied to both hierarchical and flat methodologies.

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities.

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network Perspective

The academia and industry have been pursuing network-on-chip (NoC) related research since two decades ago when there was an urgency to respond to the scaling and technological challenges imposed on intra-chip communication in SoC designs. Like any other research topic, NoC inevitably goes through its life cycle: A. it started up (2000–2007) and quickly gained traction in its own right; B. it then entered the phase of growth and shakeout (2008–2013) with the research outcomes peaked in 2010 and remained high for another four/five years; C. NoC research was considered mature and stable (2014–2020), with signs showing a steady slowdown. Although from time to time, excellent survey articles on different subjects/aspects of NoC appeared in the open literature, yet there is no general consensus on where we are in this NoC roadmap and where we are heading, largely due to lack of an overarching methodology and tool to assess and quantify the research outcomes and evolution. In this paper, we address this issue from the perspective of three specific complex networks, namely the citation network, the subject citation network, and the co-authorship network. The network structure parameters ( e.g. , modularity, diameter, etc. ) and graph dynamics of the three networks are extracted and analyzed, which helps reveal and explain the reasons and the driving forces behind all the changes observed in NoC research over 20 years. Additional analyses are performed in this study to link interesting phenomena surrounding the NoC area. They include: (1) relationships between communities in citation networks and NoC subjects, (2) measure and visualization of a subject’s influence score and its evolution, (3) knowledge flow among the six most popular NoC subjects and their relationships, (4) evolution of various subjects in terms of number of publications, (5) collaboration patterns and cross-community collaboration among the authors in NoC research, (6) interesting observation of career lifetime and productivity among NoC researchers, and finally (7) investigation of whether or not new authors are chasing hot subjects in NoC. All these analyses have led to a prediction of publications, subjects, and co-authorship in NoC research in the near future, which is also presented in the paper.

Design of energy and EDP efficient 1-bit full subtractor based divider circuits for computing systems

In today's very large scale integration (VLSI) systems, energy efficiency, power consumption per clock frequency is major concern in SoC designs. The two performance parameters, namely, the power and delay, which generally make a decision regarding energy metric of the system. In this paper, a 10T (Transistor) full subtractor is proposed and compared between various one bit full subtractor (OBFS) circuits with fewer transistor count. From the results, it is observed that, the proposed 10T OBFS circuit achieves savings of more than 48% in delay, 49% in energy consumption, and 74% in energy delay product (EDP) when compared with complementary metal oxide semiconductor (CMOS) transistor scheme and 20T OBFS. Similarly, the 14T OBFS circuit achieves savings of more than 40% in power, energy consumption, and EDP when compared with the 10T OBFS scheme and other designs. The proposed 10 transistor full subtractor based divider circuit is power, energy, and EDP efficient.

Design of a CMOS Lineal Hall Sensor Front‐End Working in Current Mode with Programmable Gain Stage for Power Specific Chip

With the continuous intelligentization of power systems, the demand for the integration of digital chips and sensor chips such as the Internet of Things is also increasing. A CMOS lineal magnetic Hall sensor front‐end working in current mode with programmable gain stage is designed and implemented with SMIC 55 nm standard CMOS technology. By using a spinning‐current technique, chopper technique, and digital calibration technique to eliminate the offset voltage and nonlinearity, this magnetic Hall sensor can be easily integrated into digital systems like SoCs. This work has already finished the circuit simulation and layout design, and all simulation indicators basically reach the expected value. The maximum gain of proposed sensor systems can be up to 33.9 dB. The total power is less than 4 mW. And the total area is less than 0.113 μm2. The magnetic Hall sensor can be easily integrated into chips such as the power Internet of Things to form a single‐chip‐level SoC design, which is mainly used in applications such as circuit breakers and electric energy measurement.

Software and hardware co-simulation verification platform for navigation SoC

This paper proposes a software and hardware co-simulation verification platform suitable for satellite navigation SoC chips. The specific implementation scheme is described, and the final simulation results are given. Software simulation is written in c and assembly language, using a complete software compilation and debugging tool chain, hardware simulation is built based on verification methodology, SoC design code is written by verilog, and the software and hardware are coordinated through the VCS compiler to achieve information interaction, and then a universal simulation platform with fast speed, high authenticity and convenient debugging is realized. The simulation results show that the navigation SoC chip functions correctly.

Metadata based padring and pad multiplexing generation for microcontroller design

Defining padring and its pad interconnections is one of the most time consuming steps of a microcontroller SoC design. Also, multiple device features plus testability in limited pinout packages entails more functions shared per pin. As such, the number of padring connections and complexity exponentially grows at each new design. This paper describes a methodology to configure pad connections and select correct pad cells. The methodology works out technology and function definitions for each pin using new and previous designs data stored in a metadata database in order to generate the padring RTL code for the SoC. This methodology was proven with Freescale microcontrollers, among them to check the padring connection of the commercial microcontroller MC9S08MP16 [1], and was used to implement both MC9S08QB8 [2] and MC9S08SC4 [3] microcontrollers, which resulted in reduced design time in order of 10 folds, along with high quality generated RTLs.

Design Of An Improved And Robust Asynchronous Wrapper (Aw) For FPGA Applications

Contemporary digital systems must be based on the “System-on-Chip – SoC” concept. An interesting style for SoC design is the GALS paradigm (Globally Asynchronous, Locally Synchronous), which can be used to implement circuits in FPGAs (Field Programmable Gate Arrays). However the implementation of asynchronous interfaces (asynchronous wrapper – AW) constitutes a major drawback for this kind of devices. Although there is a typical AW design style, which is based on asynchronous controllers providing communication between modules (called ports), port controllers are subject to essentialhazard when implemented in FPGAs. In this context, this paper proposes a new asynchronous GALS wrapper architecture, suitable for implementations in any kind of FPGAs. The proposed port controllers showed to be essential-hazard-free, not needing any special cares in implementation concerning to LUTs choice. Additional advantages of the proposed architecture are: total autonomy that synchronous modules achieve when interacting with the asynchronous wrapper; the ports can be synthesized in the direct mapping style (so without knowledge of asynchronous logic synthesis); and the ports interact with environment in Ib/Ob Mode, not needing a timing analysis. Simulation results show the applicability of the proposed architecture and lead to its practical implementations in FPGAs.

Approach for a Safe-SoC for Cyber-physical Application according to IEC 61508

Using electronic systems to control complex applications has found its way into nearly all technical and industrial areas during the last four decades. Today, in addition to system size, reduced system costs, optimized energy consumption and high reliability or safety, the aspects of functional safety are increasingly in the focus of many applications. Especially concerning safe embedded cyber-physical systems, which is favored by increasing integration of components, these aspects are of central importance. This article describes a consistently safety 1oo2 SoC architecture model (a miniaturized safety system on a chip) based on a modified software comparator architecture. The design and realization of the safety SoC, according to IEC 61508, are also presented.

Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective

Logic locking is a holistic solution to counter manufacturing threats, such as intellectual property (IP) piracy and overbuilding at the hardware level. However, years of research has exposed various flaws in locking, including a Boolean satisfiability (SAT)-based attack. Consequently, several SAT-resilient locking techniques, such as SARLock, Anti-SAT, and SFLL have been proposed, although certain instances of them have also been broken by a class of attacks, called removal attack. In this article, we approach logic locking by leveraging well-known principles from very large-scale integration (VLSI) testing and elicit logic locking properties that dictate the resilience of a locking technique against different attacks. We present a revised version of SFLL, namely SFLL-rem, that not only retains all security properties of SFLL, delivering resilience to all the state-of-the-art attacks SFLL can thwart, but also to the latest removal attacks that broke some SFLL instances. Further, we develop a security-aware CAD framework integrated with industry tools that incurs only −1.5%, 0%, and 4.13% overhead for power, performance, and area, respectively. We demonstrate a silicon implementation of SFLL-rem on ARM Cortex-M0 microprocessor in 65 nm. Moreover, we provide a framework for an SoC designer to customize logic locking based on the SoC blocks and their threat models; this is illustrated by locking a multimillion-gate SoC provided by DARPA, and taking the SoC all the way to GDSII layout.

RoadNet-RT: High Throughput CNN Architecture and SoC Design for Real-Time Road Segmentation

In recent years, convolutional neural network (CNN) has gained popularity in many engineering applications especially for computer vision. In order to achieve better performance, more complex structures and advanced operations are incorporated into neural networks, which results in very long inference time. For time-critical tasks such as autonomous driving and virtual reality, real-time processing is fundamental. In order to reach real-time processing speed, a lightweight, high-throughput CNN architecture namely RoadNet-RT is proposed for road segmentation in this article. It achieves 92.55% MaxF score on KITTI road segmentation dataset. The inference time is about 9 ms per frame when running on GTX 1080 GPU. Comparing to the state-of-the-art network, RoadNet-RT speeds up the inference time by a factor of 17.8 at the cost of only 3.75% loss in accuracy. What is more, on CamVid dataset its accuracy is 92.98%. Several techniques such as depthwise separable convolution and non-uniformed kernel size convolution are optimized in the hardware accelerator design. The proposed CNN architecture has been successfully implemented on a ZCU102 MPSoC FPGA that achieves the computation capability of 331 GOPS using INT8 quantization. The system throughput reaches 196.7 frames per second with input image size of 280 × 960 . The source code is published at https://github.com/linbaiwpi/RoadNet-RT.

A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

SummaryHigh performance system‐on‐chip (SoCs) designs have led to high‐density integrated circuits using field programmable gate arrays (FPGAs) for rapid prototyping and reconfigurable digital circuits. Using FPGA reconfigurability, it is possible to design a configurable network‐on‐chip (NoC) for different applications. NoC architectures provide efficient communication infrastructures for implementing very large SoCs. In this article, we propose HiFMP, a high‐performance FPGA‐based multicrossbar prioritized NoC router. The aim followed by the proposed router is designing a low‐power NoC router with high performance in terms of energy‐efficiency, network throughput, area, and latency for efficient FPGA realization. HiFMP is a parameterizable router, and is effectively used for an FPGA‐based NoC with mesh topology. Performance evaluations include network‐level analysis and hardware exploration; the results demonstrate the effectiveness and high performance of HiFMP in terms of latency, throughput, power consumption, and area, comparing with the existing related architectures.