Abstract
Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.
Highlights
Current Many-Core System-on-Chip designs exploit the computation power and parallelism available for dynamic workload systems such as mobile smartphones, IoT, embedded devices, desktop, and data centers
We present the rest of this work as follows: Section 2 explains the motivation for a Software-Defined Network-on-Chip (SDNoC) approach
We focus on NoC management problems, and we leave aside programming and logic implementation issues to focus on the communication processes optimizations
Summary
Current Many-Core System-on-Chip designs exploit the computation power and parallelism available for dynamic workload systems such as mobile smartphones, IoT, embedded devices, desktop, and data centers. A Many-Core System-on-Chip has a number from tens to thousands of processing cores and memories interconnected by an on-Chip network. The processing cores vary from CPU, GPU, Intellectual Property (IP), programmable hardware, and specialized neuromorphic hardware for artificial intelligence, among many others. This trend indicates the importance of accelerating new chips’ design by using an NoC solution from companies that have proven their products in the marketplace. Arteris is currently the only significant player in the NoC scene; this leaves a fertile path for innovation and creating solutions for recent market niches
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