Test power and area optimized logic built-in self-test with higher fault coverage for automobile SoCs

Abstract

With higher computerization in the automobile stream, the built-in self-test is essential for high quality and high-reliability SoCs. BIST is a self-testing method for the larger SoC designs. This paper presented a new logic BIST architecture with a new weighted pseudorandom TPG and a hybrid test point allocation method. The proposed architecture is optimized for the physical factors such as the test power consumption, the fault coverage, the WSA, and the area overhead during the scan-in testing phase. The proposed method initiated the sharing concept of flip-flops in the test gate strategies to optimize the area overhead. It also demonstrated the test point allocation enabled using the weighted patterns to enhance the fault coverage throughout the scan chains. The primary seeds are flipped and sorted into weighted patterns to obtain the transition delay faults as their complete fault coverage. Simulation works are examined in SilTerra 0.13 μm on Mentor Graphics IC design tool. Experimental results of the logic BIST architecture are executed, and the results are tabulated. The performance comparison of proposed logic BIST with the existing BIST architectures is also analyzed. Consequently, the proposed BIST is employed in the automobile SoC as an application. The ADAS automobile SoC scan circuits were tested in this paper for their self-testing phenomenon. The tabulated results for the physical factors showed that valuable improvements could be accomplished using the proposed BIST compared with the existing authors.