Single-slope ADC Research Articles

An 11-bit low power column-parallel single slope ADC with comparator toggle prediction technique for CMOS image sensor

This paper proposes an 11-bit low power column-parallel SS ADC with DCDS for CMOS image sensors. The proposed SS ADC reduces the power consumption in three ways. Firstly, using a combination of coarse and fine quantization can reduce power consumption of counter. Secondly, changing the operation state can remove the bit width inverter. Thirdly, the comparator power is reduced by making each column of comparators switch off after the end of the comparison function. The proposed ADC is fabricated in a 110 nm 1P4M CMOS technology and has a DNL of +0.64/−0.54 LSB and an INL of +0.04/−6.7 LSB at a sampling frequency of 29.9 kS/s. The single column SS ADC has the power consumption ranging from 39.6 μW to 74.87 μW. Compared with the conventional SS ADC, the minimum and the maximum reduction of the power consumption are 20.1 % and 43.8 %, respectively. The average power saving is 34.5 %.

A self-adaptive correlated multiple sampling technique based on single-slope ADC for low-noise CMOS image sensors

This paper presents a self-adaptive correlated multiple sampling (SACMS) technique for low-noise CMOS image sensors. Compared to the traditional correlated multiple sampling (TCMS), SACMS technique adds a pre-determination stage to determine the brightness of the pixel, reducing the 4 large-range ramps to 3 small-range ramps and 1 large-range ramp when quantizing the signal. For dark pixels, the signal is quantized using small-range ramps with short sampling interval to reduce low-frequency noise. For bright pixels, the CMS operation is turned off and the signal is quantized only once in the large-range ramp to improve the frame rate. Simulation results demonstrate that, for dark pixels, SACMS achieves a minimum readout noise of 84.22μVrms at eight times analog gain, compared to 108.76μVrms with TCMS, representing an approximately 21.7 % improvement in noise suppression. Additionally, the sampling rate of the SSADC employing SACMS technique is 36.36 kHz, while the sampling rate of the SSADC using TCMS technique is 21 kHz.

A 28.9–38.8 μW dual-mode 10-bit column parallel single-slope ADC with minimum voltage feedback for CMOS image sensors

A dual-mode low-power column parallel single-slope (SS) ADC incorporating Minimum Voltage Feedback (MVF) is proposed for CMOS image sensors. When it works in low-power mode, the ADC utilizes a minimum voltage feedback approach and a dynamic bias structure to minimize the power consumption after the ramp signal surpasses the minimum voltage of a row. In its acceleration mode, it uses the minimum voltages extracted by the MVF circuit to improve the conversion speed. A 10-bit SS ADC with MVF was designed in a 0.18 μm CMOS process. The simulations have been performed to validate the proposed idea. The simulation results show that DNL and INL of the ADC are +0.124/-0.126 LSB and +0.15/-0.12 LSB, respectively. Moreover, the SNDR achieves 61.4 dB, the SFDR is 72.04 dB and the ENOB is 9.9 bit. Under the clock frequency of 100 MHz and the power supply of 3.3 V/1.8 V in the low-power mode, the simulated power consumption of the ADC ranges between 28.9 and 38.8 μW/column, with the column parallel comparator and ramp generator contributing to power reductions of up to 33.0 % and 53.5 %, respectively. The conversion time experiences a notable decrease of up to 65.4 % in the acceleration mode. The power consumption of the added MVF circuit is only 0.15 μW/column.

A 12~14-Bit SAR-SS Hybrid ADC with SS Bit Shifting Resolution Reconfigurable Method for Bio-Signal Processing

This paper presents a low-power, high-resolution reconfigurable hybrid ADC for bio-electrical signal processing. The proposed ADC contains a SAR ADC for the most significant bit (MSB) and a single-slope ADC for the least significant bit (LSB). To solve the issue of exponentially increasing sampling speed based on the resolution of the single-slope ADC, the SAR ADC is designed to be reconfigurable with a resolution of 8–10-bit, while the single-slope ADC is configured with a resolution of 4-bit. To achieve this resolution reconfiguration, the bit shifting method is proposed and implemented with reconfigurable SAR logic circuit and 4-bit single-slope digital ramp generator. Measurement results demonstrate the power consumption of 34.0 uW, which includes analog power of 23.8 uW and digital power of 10.2 uW, INL/DNL of ±3.5 LSB and −1.0/+2.5 LSB. The ENOB and FoM are measured to be 10.8 bits and 53 fJ/step, respectively.

A 12-bit single slope ADC with multi-step structure and ramp calibration technique for image sensors

This paper presents a novel multi-step single slope analog to digital converter (MS SS ADC). The proposed ADC splits the 12-bit conversion into 3 steps, including 1-bit half section decision, 4-bit coarse conversion, and finally 8-bit fine conversion with 1-bit redundancy. The conversion step is substantially reduced from conventional 4096 to 276. The linearity of the ADC is guaranteed by a stable common mode voltage of the comparator varying only within 31.25 mV. Moreover, two high-accuracy ramp calibration techniques are utilized to correct the current variation in the fine ramp and the slope error between the coarse and fine ramps. A hybrid comparator is utilized in the ADC to save power while maintaining the performance. The ADC is designed and simulated in 0.18 μm CMOS process with 7.5 μm width. The differential nonlinearity and integral nonlinearity of the proposed ADC are reduced from +0.3/-1 LSB and +3.1/-2.55 LSB to +0.3/-0.3 LSB and +1/-0.45 LSB at 61.7 kS/s sample rate by the calibrations.

A multichannel readout integrated circuit with column-wise pseudo differential extended counting ADCs for an uncooled infrared focal plane array based on silicon diodes

This paper presents a multichannel readout integrated circuit (ROIC) with column-wise extended counting (EC) ADCs, which is targeted toward silicon diode uncooled infrared focal plane arrays (IRFPA). The column ADC features a direct connection with the detectors without extra pre-amplifiers. The ROIC incorporates 9-bit folding integration ADCs for coarse conversion and 5-bit single-slope ADCs for fine conversion. A pseudo-differential architecture combined with blind pixels is adopted to cancel even-order distortion. To improve linearity without increasing power consumption, a ping-pong integrator is adopted to reduce reset time by charging alternatively. A prototype consisting of 32 columns is fabricated in 180 nm 1P5M CMOS process for verification. The power consumption of one column is 50.5 μW. According to the measurement results, the input-referred noise is 1.21 LSB (2.36 μVrms), and the peak SNR is 82.5 dB. The INL and DNL are +2.43/-2.21 LSB and +0.33/-0.31 LSB, separately.

A high-speed 13-bit two-step single-slope ADC for large array CMOS image sensors

This paper proposes a 13-bit two-step single-slope (TS-SS) ADC for high-speed CMOS image sensors. The ADC design method is based on the ideas of time sharing and time compression, moves the fine conversion time to the coarse conversion time period, and eliminates the traditional method's time redundancy issue. The differential nonlinearity (DNL) and integral nonlinearity (INL) are simulated to be +0.8/-0.8 LSB and +2.1/-3.5 LSB, respectively, for the 55 nm 1P4M CMOS process. 512 ns is the conversion time of the 13-bit ADC. The power consumption is 47 μW, and the effective number of bits (ENOB) is 11.33 bits. In comparison to existing advanced ADCs, the method proposed in this paper can increase the ADC conversion rate by more than 60% while maintaining low power consumption and high precision, thereby providing theoretical support for the readout and conversion of high-speed and high-precision CMOS image sensors.

A Low Power ROIC with Extended Counting ADC Based on Circuit Noise Analysis for Sensor Arrays in IoT System

As the Internet of Things (IoT) is rapidly integrated into our daily life, the demand for high performance readout integrated circuit (ROIC) design for sensor arrays is boosting. This paper presents a low power, low noise ROIC with 14-bit column-parallel extended counting (EC) ADCs for sensor arrays targeting the IoT applications. The proposed EC-ADC adopts a pseudodifferential architecture to cancel even-order nonlinearity. The analog front-end is a G m stage, which employs a current-reuse topology to boost the transconductance and reduce noise without increasing current consumption. The upper 9-bit conversion is implemented during integration, and the residual voltage is converted by a 5-bit single-slope (SS) ADC, where the comparator is reused. A ping-pong integrator is proposed to reduce the reset time and improve linearity, eliminating the power-hungry CTIA structure. The ROIC is designed in 0.18 μm 1P5M CMOS process for a 640 × 480 sensor array. Power consumption of the ROIC is 33 mW, and each column ADC consumes 40.1 μW. Simulation results show an input-referred noise of 0.89 LSB (1.74 μVrms), an integral nonlinearity of +0.92/-0.70 LSB, an ENOB of 12.87 bits, and a FoM of 131.1 fJ/step.

A LoC Ion Imaging Platform for Spatio-Temporal Characterisation of Ion-Selective Membranes.

In this paper, a complete Lab-on-Chip (LoC) ion imaging platform for analysing Ion-Selective Membranes (ISM) using CMOS ISFET arrays is presented. An array of 128 × 128 ISFET pixels is employed with each pixel featuring 4 transistors to bias the ISFET to a common drain amplifier. Column-level 2-step readout circuits are designed to compensate for array offset variations in a range of up to ±1 V. The chemical signal associated with a change in ionic concentration is stored and fed back to a programmable gain instrumentation amplifier for compensation and signal amplification through a global system feedback loop. This column-parallel signal pipeline also integrates an 8-bit single slope ADC and an 8-bit R-2R DAC to quantise the processed pixel output. Designed and fabricated in the TSMC 180 nm BCD process, the System-on-Chip (SoC) operates in real time with a maximum frame rate of 1000 fps, whilst occupying a silicon area of 2.3 mm × 4.5 mm. The readout platform features a high-speed digital system to perform system-level feedback compensation with a USB 3.0 interface for data streaming. With this platform we show the first reported analysis and characterisation of ISMs using an ISFETs array through capturing real-time high-speed spatio-temporal information at a resolution of 16 μm in 1000 fps, extracting time-response and sensitivity. This work paves the way of understanding the electrochemical response of ISMs, which are widely used in various biomedical applications.

A low-power high-quality CMOS image sensor using 1.5 V 4T pinned photodiode and dual-CDS column-parallel single-slope ADC

This paper presents a low-power high-quality CMOS image sensor (CIS) using 1.5 V 4T pinned photodiode (4T-PPD) and dual correlated double sampling (dual-CDS) column-parallel single-slope ADC. A five-finger shaped pixel layer is proposed to solve image lag caused by low-voltage 4T-PPD. Dual-CDS is used to reduce random noise and the nonuniformity between columns. Dual-mode counting method is proposed to improve circuit robustness. A prototype sensor was fabricated using a 0.11 µm CMOS process. Measurement results show that the lag of the five-finger shaped pixel is reduced by 80% compared with the conventional rectangular pixel, the chip power consumption is only 36 mW, the dynamic range is 67.3 dB, the random noise is only 1.55 e– rms, and the figure-of-merit is only 1.98 e–·nJ, thus realizing low-power and high-quality imaging.

A low-noise readout circuit design for multi-bit quanta image sensor

This paper presents a novel readout circuit based on low-noise charge transfer amplifier (LCTA) to suppress the readout noise in multi-bit quanta image sensor. A switched capacitor circuit is used in LCTA to reduce the kT/C noise introduced by its load capacitor, and make the noise from ADC further suppressed due to the increase of its output swing. The digital correlated double sampling of single-slope ADC is used to eliminate the fixed noise in LCTA. The low noise readout circuit is implemented by a 110 nm CMOS process. The simulation results show that the random noise of LCTA is reduced by 19% at a gain of 2 V/V compared to the conventional differential charge transfer amplifier. The increased output swing reduces the random noise power of ADC by 61%. In addition, the LCTA equivalent input fixed noise with 29.8 μVrms is eliminated. The proposed low-noise readout circuit improves the signal-to-noise ratio by 4.37 dB at small-signal conditions.

A self-compensated approach for ramp kickback noise in CMOS image sensor column parallel single slope ADC

A new CMOS image sensor column parallel ADC circuit structure for suppressing the kickback noise of the single slope comparators is proposed in this paper. In order to suppress the kickback noise of the original node, the crosstalk of the shared ramp reference is compensated by detecting the column ramp signal jumping, and the transmission of the noise on the shared reference line is blocked. The proposed approach has been verified and experimented in a 3072(H) × 2560(V) CMOS image sensor based on 55 nm 1P4M CMOS process, and the sensor achieves 12bit precision column parallel digital quantization. In the worst case, when 1 to 1000 columns are flipped simultaneously, the kickback noise can be reduced to less than 1LSB and compensated quickly without additional power consumption and area. The measurement results show that the single slope ADC can be operated at 500 MHz and achieved 4.6μs digital correlated double sampling row time for a 12-bit linear A/D conversion, the DNL is controlled within ±0.48LSB, the INL is not more than ±4LSB, and the SNR is up to 71 dB. It is important that the power consumption of each column is only 24 μW.

An Indirect Time-of-Flight SPAD Pixel With Dynamic Comparator Reuse for a Single-Slope ADC

An Indirect Time-of-Flight SPAD Pixel With Dynamic Comparator Reuse for a Single-Slope ADC

An Ultra-High Frame Rate Ion Imaging Platform Using ISFET Arrays With Real-Time Compression.

In this paper, a Lab-on-Chip platform with ultra-high throughput and real-time image compression for high speed ion imaging is presented. The sensing front-end comprises of a CMOS ISFET array with sensors biased in velocity saturation for a linear pH-to-current conversion and high spatial and temporal resolution. An array of 128 × 128 pixels is designed with a pixel size of 13.5 μm × 10.5 μm. In-pixel reset switches are applied for offset compensation, by asynchronously resetting the floating gate of the ISFET to a known fixed potential. Additionally, each row of pixels is processed by a current mode signal pipeline with auto zeroing functionality to remove fixed pattern noise, followed by an on-chip 1 MS/s 8-bit row-parallel single slope ADC. Fabricated in standard TSMC 180 nm BCD process, the entire system-on-chip occupies a silicon area of 2 mm × 2 mm, and achieves a frame rate of 6100 fps (7800 fps from simulation). A high speed 25 ms-latency readout platform based on a USB 3.0 interface and standard JPEG is presented for real-time ion imaging and image compression respectively, while an optimised JPEG algorithm is also designed and verified for a higher compression ratio without sacrificing image quality. We demonstrate real-time ion image visualisation by sensing high speed ion diffusion at 6100 fps, which is more than two times faster than the current state-of-the-art.

A 51-pJ/Pixel 33.7-dB PSNR 4× Compressive CMOS Image Sensor With Column-Parallel Single-Shot Compressive Sensing

This article presents a CMOS image sensor (CIS) with column-parallel single-shot compressive sensing (CS) for always-on Internet-of-Things (IoT) application, which achieves an energy efficiency of 51 pJ/pixel, while maintaining high image quality of PSNR > 33.7 dB and SSIM > 0.89. This is enabled by an energy-efficient encoder, which replaces a densely populated CS encoding matrix with a highly sparse pseudo-diagonal one. Since the proposed column-parallel CS encoder can be implemented directly at pixel outputs with an energy-efficient switched-capacitor matrix multiplier, data compression is achieved prior to the pixel digitization, thereby greatly reducing ADC power, data size, and I/O power. The energy efficiency of the image sensor is further improved by using dynamic single-slope ADCs. A prototype VGA image sensor implemented in a 110-nm CMOS process consumes only 0.7 mW at 45 frames/s. The corresponding energy per pixel (51 pJ/pixel) amounts to more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times $ </tex-math></inline-formula> improvement over the previous low-energy benchmark for CS image sensors.

Low‐power column counter with a logical‐shift algorithm for CMOS image sensors

The authors propose a column counter that uses a logical-shift algorithm in column-parallel single-slope ADCs for low-power CMOS image sensors. The proposed column counter lowers power consumption by reducing the amount of internal toggling nodes and parasitic capacitance. Simulation results showed a 32% reduction in power consumption and a 60% reduction in the power-delay product compared to a conventional up/down counter.

A 10-bit reconfigurable ADC with SAR/SS mode for neural recording

A dual-mode, reconfigurable ADC for neural recording application is presented in this paper. In order to quantize the extracellular action potential (EAP or spike) of neural signal, the proposed ADC works as a 10 bits successive approximation register (SAR) ADC in the normal mode to process all the raw data. In other side, to reduce dynamic power, the ADC is designed to configure as a single-slope (SS) ADC in compression mode, and only essential parts of spike waveforms are processed. Fabricated in a 0.18 µm CMOS process, the proposed ADC consumes 2.83 μW in SAR mode and 24.71 μW in SS mode at supply voltage of 1.8 V, respectively. In SAR mode, the achieved SNDR and SFDR are 60.5 dB and 75.5 dB when a Nyquist frequency input signal is received @ the sampling rate of 25 kS/s. While in SS mode, the achieved SNDR and SFDR are 57.7 dB and 60.8 dB.

In brief

PAGE 436 A novel subwavelength and low-profile element has been proposed by a group of Chinese researchers for reflected antenna array applications. A metallic hole is used to achieve smaller profile and period dimensions with the element obtaining a wide reflected phase shifting range. The results are validated with data gained from a fabricated prototype. PAGE 473 A classical expression of quantum microwaves after measurement, dependent on intrinsic correlated characteristics between measurement uncertainties and components of the microwave field, has been presented by researchers from China. The results are in agreement with experiments of entangled quantum microwaves and provide a more intuitive understanding of the wave behavior. Configuration of the proposed element. PAGE 434 A pair of researchers in China have designed and produced a slim dual-polarised antenna with omnidirectional patterns for WLAN applications. The slim structure has the advantages of light weight, convenient implementation, and easy fabrication due to the improved isolation between the two polarisations, with a rectangular loop acting as a tuner for the antenna impedance. Waveform schematics before and after measurement. PAGE 446 Improved energy harvesting efficiency in wireless sensors using a CMOS cross-couple RF rectifier has been presented by researchers in Korea. The proposed device uses a thick-oxide MOSFET to improve efficiency by reducing reversing leakage current and presents an 8% peak efficiency gain compared to conventional rectifiers. Feeding network of the proposed antenna. PAGE 438 Researchers from Taiwan have put forward a fully integrated bio-system with high sensitivity for electrochemical detection. The system measures the electrochemical characteristics using cyclic voltammetry whith the operating mechanism of the potentiostat behaving like a single-slope ADC. The system demonstrates feasibility in low-electrolyte environments. Voltage waveforms of internal nodes and output. Electrochemical detection system architecture.

A 1-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;s Ramp Time 12-bit Column-Parallel Flash TDC-Interpolated Single-Slope ADC With Digital Delay-Element Calibration

This work presents a hybrid column-parallel time-to-digital-converter interpolated (TDC) single-slope (SS) ADC with a digital delay element feedback. The proposed scheme solves the multiphase clock period matching problem in flash TDC-interpolation of SS ADCs without the use of a delay-locked-loop. The architecture employs open-loop delay elements for multiphase clock generation forming a lowered TDC radix of $1024\times128$ linescan image sensor testchip manufactured in a 0.13- $\mu \text{m}$ 1P3M CMOS process. The ADC operates at 250 MHz and achieves a 1- $\mu \text{s}$ ramp time and 4.4- $\mu \text{s}$ digital correlated double sampling row time for a 12-bit linear A/D conversion.

A FHD 1080, 120 fps CMOS image sensor with two step SS-ADC

This paper presents a full high definition 1920 × 1080 pixel, 120 frames/s CMOS image sensor with two-step single-slope (TS-SS) ADC. The column-parallel TS-SS ADC and binary subtractor are used to convert photodiode voltage to the final 10-bit digital data. Therefore, there is no need for the pixel readout, noise suppression or comparator offset cancellation circuits to be used in the columns. A new ramp signal generator is proposed to generate 32 concurrent and identical ramp signals. TS-SS ADC improves the conversion speed while reducing the power consumption level as well. The proposed image sensor has been designed using TSMC 0.18 μm 1-poly 4-metal standard process. The simulation results show that the total comparator referred noise to the FD node in 1 Hz–100 MHz range is 0.574 mV and, also the total power consumption is about 100 mW.