A self-compensated approach for ramp kickback noise in CMOS image sensor column parallel single slope ADC

Abstract

A new CMOS image sensor column parallel ADC circuit structure for suppressing the kickback noise of the single slope comparators is proposed in this paper. In order to suppress the kickback noise of the original node, the crosstalk of the shared ramp reference is compensated by detecting the column ramp signal jumping, and the transmission of the noise on the shared reference line is blocked. The proposed approach has been verified and experimented in a 3072(H) × 2560(V) CMOS image sensor based on 55 nm 1P4M CMOS process, and the sensor achieves 12bit precision column parallel digital quantization. In the worst case, when 1 to 1000 columns are flipped simultaneously, the kickback noise can be reduced to less than 1LSB and compensated quickly without additional power consumption and area. The measurement results show that the single slope ADC can be operated at 500 MHz and achieved 4.6μs digital correlated double sampling row time for a 12-bit linear A/D conversion, the DNL is controlled within ±0.48LSB, the INL is not more than ±4LSB, and the SNR is up to 71 dB. It is important that the power consumption of each column is only 24 μW.