Abstract
This work presents a hybrid column-parallel time-to-digital-converter interpolated (TDC) single-slope (SS) ADC with a digital delay element feedback. The proposed scheme solves the multiphase clock period matching problem in flash TDC-interpolation of SS ADCs without the use of a delay-locked-loop. The architecture employs open-loop delay elements for multiphase clock generation forming a lowered TDC radix of $1024\times128$ linescan image sensor testchip manufactured in a 0.13- $\mu \text{m}$ 1P3M CMOS process. The ADC operates at 250 MHz and achieves a 1- $\mu \text{s}$ ramp time and 4.4- $\mu \text{s}$ digital correlated double sampling row time for a 12-bit linear A/D conversion.
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