A Low Power ROIC with Extended Counting ADC Based on Circuit Noise Analysis for Sensor Arrays in IoT System

Abstract

As the Internet of Things (IoT) is rapidly integrated into our daily life, the demand for high performance readout integrated circuit (ROIC) design for sensor arrays is boosting. This paper presents a low power, low noise ROIC with 14-bit column-parallel extended counting (EC) ADCs for sensor arrays targeting the IoT applications. The proposed EC-ADC adopts a pseudodifferential architecture to cancel even-order nonlinearity. The analog front-end is a G m stage, which employs a current-reuse topology to boost the transconductance and reduce noise without increasing current consumption. The upper 9-bit conversion is implemented during integration, and the residual voltage is converted by a 5-bit single-slope (SS) ADC, where the comparator is reused. A ping-pong integrator is proposed to reduce the reset time and improve linearity, eliminating the power-hungry CTIA structure. The ROIC is designed in 0.18 μm 1P5M CMOS process for a 640 × 480 sensor array. Power consumption of the ROIC is 33 mW, and each column ADC consumes 40.1 μW. Simulation results show an input-referred noise of 0.89 LSB (1.74 μVrms), an integral nonlinearity of +0.92/-0.70 LSB, an ENOB of 12.87 bits, and a FoM of 131.1 fJ/step.