Single-photon Avalanche Diode Pixel Research Articles

A 3.06 μm Single-Photon Avalanche Diode Pixel with Embedded Metal Contact and Power Grid on Deep Trench Pixel Isolation for High-Resolution Photon Counting.

In this study, a 3.06 μm pitch single-photon avalanche diode (SPAD) pixel with an embedded metal contact and power grid on two-step deep trench isolation in the pixel is presented. The embedded metal contact can suppress edge breakdown and reduce the dark count rate to 15.8 cps with the optimized potential design. The embedded metal for the contact is also used as an optical shield and a low crosstalk probability of 0.4% is achieved, while the photon detection efficiency is as high as 57%. In addition, the integration of a power grid and the polysilicon resistor on SPAD pixels can help to reduce the voltage drop in anode power supply and reduce the power consumption with SPAD multiplication, respectively, in a large SPAD pixel array for a high-resolution photon-counting image sensor.

Performance of Active-Quenching SPAD Array Based on the Tri-State Gates of FPGA and Packaged with Bare Chip Stacking.

The performance of an active-quenching single-photon avalanche diode (SPAD) array that is based on the tri-state gates of a field programmable gate array (FPGA) is presented. The array is implemented by stacking a bare 4 × 4 N-on-P SPAD array on a bare FPGA die, and the electrodes of the SPAD pixels and the I/O ports of the FPGA are connected through wire bonding within the same package. The active quenching action on each SPAD pixel is performed by using the properties of the tri-state gates of the FPGA. Digital signal processing, such as pulse counters, data encoders, and command interactions, is also performed by using the same FPGA. The breakdown voltage of the SPAD pixels, with an active area of 60 μm × 60 μm, is 47.2-48.0 V. When the device is reverse biased at a voltage of ~50.4 V, a response delay of ~50 ns, a dead time of 157 ns, a dark count rate of 2.44 kHz, and an afterpulsing probability of 6.9% are obtained. Its peak photon detection probability (PDP) reaches 17.0% at a peak wavelength of 760 nm and remains above 10% at 900 nm. This hybrid integrated SPAD array is reconfigurable and cost effective.

SPAD Pixel With Sub-NS Dead-Time for High-Count Rate Applications

Single-photon avalanche diode (SPAD) exploitation in high-flux applications is often hindered by the trade-off between the SPAD dead-time and afterpulsing probability. In this paper, we present the architecture and the experimental characterization of two chips including a novel SPAD sensing, and readout scheme designed to minimize dead-time (1.78 ns and 0.93 ns respectively) and afterpulsing probability (0.14% maximum). We have coupled this architecture with high-performance SPADs obtaining an extremely stable dead-time (6.44 ps_rms jitter) that can be easily regulated through an external voltage. Thanks to its compact size, this novel pixel architecture can be easily integrated within high-resolution SPAD arrays for GHz applications.

High-Speed Active Quench and Reset Circuit for SPAD in a Standard 65 nm CMOS Technology

A compact high-speed active quench and reset (AQR) circuit integrated with a p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /n-well single-photon avalanche diode (SPAD) is designed and fabricated in a standard 65 nm CMOS technology. The post-layout simulations showed that the quenching time for this AQR circuit is only 0.1 ns, and the smallest dead time is 3.35 ns which corresponds a maximum count rate of ~300 Mcps. The measurements showed that the SPAD pixel achieved a dark count rate of 21 kHz, a peak photon detection probability of 23.8% at a 420 nm wavelength and a timing jitter of 139 ps (using a 405 nm pulsed laser) when the excess voltage was 0.5 V. Also, due to the short quenching time, negligible afterpulsing was observed during the measurements.

A Scaling Law for SPAD Pixel Miniaturization.

The growing demands on compact and high-definition single-photon avalanche diode (SPAD) arrays have motivated researchers to explore pixel miniaturization techniques to achieve sub-10 μm pixels. The scaling of the SPAD pixel size has an impact on key performance metrics, and it is, thereby, critical to conduct a systematic analysis of the underlying tradeoffs in miniaturized SPADs. On the basis of the general assumptions and constraints for layout geometry, we performed an analytical formulation of the scaling laws for the key metrics, such as the fill factor (FF), photon detection probability (PDP), dark count rate (DCR), correlated noise, and power consumption. Numerical calculations for various parameter sets indicated that some of the metrics, such as the DCR and power consumption, were improved by pixel miniaturization, whereas other metrics, such as the FF and PDP, were degraded. Comparison of the theoretically estimated scaling trends with previously published experimental results suggests that the scaling law analysis is in good agreement with practical SPAD devices. Our scaling law analysis could provide a useful tool to conduct a detailed performance comparison between various process, device, and layout configurations, which is essential for pushing the limit of SPAD pixel miniaturization toward sub-2 μm-pitch SPADs.

Compact SPAD pixels with fast and accurate photon counting in the analog domain

A compact pixel for single-photon detection in the analog domain is presented. The pixel integrates a single-photon avalanche diode (SPAD), a passive quenching & active recharging circuit (PQARC), and an analog counter for fast and accurate sensing and counting of photons. Fabricated in a standard 0.18 µm CMOS technology, the simulated and experimental results reveal that the dead time of the PQARC is about 8 ns and the maximum photon-counting rate can reach 125 Mcps (counting per second). The analog counter can achieve an 8-bit counting range with a voltage step of 6.9 mV. The differential nonlinearity (DNL) and integral nonlinearity (INL) of the analog counter are within the ± 0.6 and ± 1.2 LSB, respectively, indicating high linearity of photon counting. Due to its simple circuit structure and compact layout configuration, the total area occupation of the presented pixel is about 1500 μm2, leading to a high fill factor of 9.2%. The presented in-pixel front-end circuit is very suitable for the high-density array integration of SPAD sensors.

Investigation of random telegraph signal in two junction layouts of proton irradiated CMOS SPADs

This paper focuses on the understanding of the Random Telegraph Signal (RTS) in Single-Photon Avalanche Diodes (SPAD). We studied the RTS of two different SPAD layouts, designed and implemented in a 150-nm CMOS process, after proton irradiation. The two structures are characterized by different junction types: the first structure is constituted by a P+/Nwell junction, while the second is formed by a Pwell/Niso junction. RTS occurrence has been measured in about one thousand SPAD pixels and the differences addressed in two layouts are motivated and discussed. Hypotheses on the RTS origin are drawn by analyzing the RTS time constants and the RTS occurrence evolution as a function of the annealing temperature.

Silicon photomultiplier detector with multipurpose in-pixel electronics in standard CMOS technology

This paper presents a monolithic avalanche diode array designed in a commercial AMS 350 nm high-voltage CMOS (HV-CMOS) process. This monolithic detector comprises a single photon avalanche diode (SPAD), active quenching circuit and readout electronics. The SPAD consists of a p+ diffusion/n-well junction surrounded by a shallow p-well acting as a guard ring to prevent edge breakdown. The monolithic detector has a matrix of 20 × 15 pixels. The size of one SPAD pixel is 38 × 92 μm2. One pixel defined as SPAD and readout electronics has a total size of 115 × 111 μm2 with a fill factor = 24.3% and a chip size of about 2.8 × 2.6 mm2.

A 15 × 15 single photon avalanche diode sensor featuring breakdown pixels extraction architecture for efficient data readout

This paper proposes a breakdown pixels extraction architecture for single photon avalanche diode (SPAD) based faint light detection systems. The proposed extraction circuit detects the breakdown pixels and only their addresses are readout. Therefore, under the faint light environment, this SPAD-based sensor significantly improves the data readout efficiency. In addition, since the readout sequence is 4× faster than that of the conventional architecture in the dark condition, the proposed system does not need an independent on-chip event detection circuit that consumes additional area and power. A test-of-concept chip with a 15 × 15 SPAD pixels array was fabricated in a 0.18 µm 1P5M standard CMOS process and pinhole diffraction patterns were successfully captured thanks to the high sensitivity of the SPAD sensor. Under the faint light condition, a high-speed readout is verified by measurement and the robustness of the proposed architecture is successfully demonstrated.

Flexible ultrathin-body single-photon avalanche diode sensors and CMOS integration.

We proposed the world's first flexible ultrathin-body single-photon avalanche diode (SPAD) as photon counting device providing a suitable solution to advanced implantable bio-compatible chronic medical monitoring, diagnostics and other applications. In this paper, we investigate the Geiger-mode performance of this flexible ultrathin-body SPAD comprehensively and we extend this work to the first flexible SPAD image sensor with in-pixel and off-pixel electronics integrated in CMOS. Experimental results show that dark count rate (DCR) by band-to-band tunneling can be reduced by optimizing multiplication doping. DCR by trap-assisted avalanche, which is believed to be originated from the trench etching process, could be further reduced, resulting in a DCR density of tens to hundreds of Hertz per micrometer square at cryogenic temperature. The influence of the trench etching process onto DCR is also proved by comparison with planar ultrathin-body SPAD structures without trench. Photon detection probability (PDP) can be achieved by wider depletion and drift regions and by carefully optimizing body thickness. PDP in frontside- (FSI) and backside-illumination (BSI) are comparable, thus making this technology suitable for both modes of illumination. Afterpulsing and crosstalk are negligible at 2µs dead time, while it has been proved, for the first time, that a CMOS SPAD pixel of this kind could work in a cryogenic environment. By appropriate choice of substrate, this technology is amenable to implantation for biocompatible photon-counting applications and wherever bended imaging sensors are essential.

Afterpulsing Characteristics of Free-Running and Time-Gated Single-Photon Avalanche Diodes in 130-nm CMOS

The temperature-dependent afterpulsing characteristics of single-photon avalanche diodes (SPADs) fabricated in a standard digital 130-nm CMOS technology are described. Avalanche interarrival time statistics are analyzed to obtain the afterpulsing probabilities (APs) for 81- and 110- $\mu \text{m}^{2}$ active area SPAD pixels using free running (FR) and time-gated (TG) front-end circuits. A strong reduction in AP was evident in the TG mode compared with the FR SPAD pixels. Optimal operating conditions in terms of hold-off time and temperature were found for <1% AP.

Design, characterization and analysis of a 0.35 μm CMOS SPAD.

Most of the works about single-photon detectors rely on Single Photon Avalanche Diodes (SPADs) designed with dedicated technological processes in order to achieve single-photon sensitivity and excellent timing resolution. Instead, this paper focuses on the implementation of high-performance SPADs detectors manufactured in a standard 0.35-micron opto-CMOS technology provided by AMS. We propose a series of low-noise SPADs designed with a variable pitch from 20 μm down to 5 μm. This opens the further way to the integration of large arrays of optimized SPAD pixels with pitch of a few micrometers in order to provide high-resolution single-photon imagers. We experimentally demonstrate that a 20-micron SPAD appears as the most relevant detector in terms of Signal-to-Noise ratio, enabling emergence of large arrays of SPAD.

A Monolithic Implementation of Active Inductor VLQC and Jitter Free Photon Current Detection for Bio-Luminescence SPAD Sensor

An active inductor variable load quenching circuit monolithically implemented for sensing chlorophyll fluorescence and other sensor applications like bioluminescence, tomography, and DNA fingerprints is reported for the first time in this paper. An efficient biosignal acquisition with single-photon counting facility and fast quenching and reset for Single-Photon Avalanche Diode (SPAD) is implemented in 120 nm technology. This is the first ever monolithic active inductor implementation reported for quenching and reset of SPAD pixel. It is faster compared to all previously reported AQRC and variable load quenching circuit (VLQC) monolithic implementations. Along with the principle, a detailed design is presented in 120 nm technology. Analog simulations are done using LT Spice version IV and layout is primed using Microwind 3.1. The results reveals that a 50 ps light pulse with 250 ps dead time, i.e., light pulse with repetition rate of 300 ps can be quenched and detected.

On the application of a monolithic array for detecting intensity-correlated photons emitted by different source types

It is not widely appreciated that many subtleties are involved in the accurate measurement of intensity-correlated photons; even for the original experiments of Hanbury Brown and Twiss (HBT). Using a monolithic 4 x 4 array of single-photon avalanche diodes (SPADs), together with an off-chip algorithm for processing streaming data, we investigate the difficulties of measuring second-order photon correlations g((2))(x(iota), t(iota),x, t) in a wide variety of light fields that exhibit dramatically different correlation statistics: a multimode He-Ne laser, an incoherent intensity-modulated lamp-light source and a thermal light source. Our off-chip algorithm treats multiple photon-arrivals at pixel-array pairs, in any observation interval, with photon fluxes limited by detector saturation, in such a way that a correctly normalized g((2)) function is guaranteed. The impact of detector background correlations between SPAD pixels and afterpulsing effects on second-order coherence measurements is discussed. These results demonstrate that our monolithic SPAD array enables access to effects that are otherwise impossible to measure with stand-alone detectors.

Monolithic array of 32 SPAD pixels for single-photon imaging at high frame rates

We present a single-chip monolithic array of 32 Single-Photon Avalanche Diodes (SPAD) and associated electronics for imaging at high frame rates and high sensitivity. Photodetectors, front-end circuitry and control electronics used to manage the array are monolithically integrated on the same chip in a standard 0.35 μm CMOS high-voltage technology. The array is composed of 32 “smart” pixels working in photon counting mode and functioning in a parallel fashion. Every cell comprises of an integrated SPAD photodetector, a novel quenching circuit named as Variable Load Quenching Circuit (VLQC), counting electronics and a buffer memory. Proper ancillary electronics that perform the arbitration of photon counts between two consecutive frames is integrated as well. Thanks to the presence of in-pixel memory registers, the inter-frame dead time between subsequent frames is limited to few nanoseconds. Since integration and download are performed simultaneously and the array can be addressed like a standard digital memory, the achievable maximum frame rate is very high in the order of hundreds of thousands of frame/s.

A Single-Photon Avalanche Diode Array for Fluorescence Lifetime Imaging Microscopy.

We describe the design, characterization, and demonstration of a fully integrated single-photon avalanche diode (SPAD) imager for use in time-resolved fluorescence imaging. The imager consists of a 64-by-64 array of active SPAD pixels and an on-chip time-to-digital converter (TDC) based on a delay-locked loop (DLL) and calibrated interpolators. The imager can perform both standard time-correlated single-photon counting (TCSPC) and an alternative gated-window detection useful for avoiding pulse pile-up when measuring bright signal levels. To illustrate the use of the imager, we present measurements of the decay lifetimes of fluorescent dyes of several types with a timing resolution of 350 ps.