Abstract
Single-photon avalanche diode (SPAD) exploitation in high-flux applications is often hindered by the trade-off between the SPAD dead-time and afterpulsing probability. In this paper, we present the architecture and the experimental characterization of two chips including a novel SPAD sensing, and readout scheme designed to minimize dead-time (1.78 ns and 0.93 ns respectively) and afterpulsing probability (0.14% maximum). We have coupled this architecture with high-performance SPADs obtaining an extremely stable dead-time (6.44 ps<sub>rms</sub> jitter) that can be easily regulated through an external voltage. Thanks to its compact size, this novel pixel architecture can be easily integrated within high-resolution SPAD arrays for GHz applications.
Highlights
Single-Photon Avalanche Diodes (SPADs) are singlephoton detectors employed in many applications which benefit from their sensitivity at single-photon level [1], timing resolution [2], and fast-gating capability [3]
Since some avalanche charges can be trapped by defects in the SPAD junction and released at later times, the SPAD is kept below the breakdown voltage for a time interval called hold-off time, before being reset
Afterpulsing probability depends on the SPAD structure itself, on its associated junction capacitance (Cj) and other stray capacitances at the quenching node (Cstray), and on its excess bias (VEX), which corresponds to the voltage range at the quenching node
Summary
Single-Photon Avalanche Diodes (SPADs) are singlephoton detectors employed in many applications which benefit from their sensitivity at single-photon level [1], timing resolution [2], and fast-gating capability (i.e., the possibility to be enabled and disabled with sub-nanosecond edges) [3]. Beyond limiting the afterpulsing probability, reducing the pulse charge is a fundamental step to contain the power consumption, which is one of the critical points of developing dense SPAD arrays, especially when working at high-photon fluxes (i.e., many pixels active at the same time). Under the push of the telecommunications market, a variety of high-speed gating techniques to reduce the charge per avalanche and power consumption has been developed for InGaAs/InP SPADs, improving, beyond the count rate, afterpulsing probability and detection efficiency [19][20]. The AQC presented in [25] features 6.2 ns dead-time with a larger SPAD (50 μm diameter) developed in custom technologies, with relatively low afterpulsing (5%) This AQC occupies a large area of 364 × 90 μm, being not applicable to high density SPAD arrays.
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