Abstract
This paper focuses on the understanding of the Random Telegraph Signal (RTS) in Single-Photon Avalanche Diodes (SPAD). We studied the RTS of two different SPAD layouts, designed and implemented in a 150-nm CMOS process, after proton irradiation. The two structures are characterized by different junction types: the first structure is constituted by a P+/Nwell junction, while the second is formed by a Pwell/Niso junction. RTS occurrence has been measured in about one thousand SPAD pixels and the differences addressed in two layouts are motivated and discussed. Hypotheses on the RTS origin are drawn by analyzing the RTS time constants and the RTS occurrence evolution as a function of the annealing temperature.
Highlights
This paper focuses on the understanding of the Random Telegraph Signal (RTS) in Single-Photon Avalanche Diodes (SPAD)
We observed that the RTS occurrence increases with the SPAD active area (Fig. 9) because of the higher probability for protons to interact with a larger SPAD
This work reports on the RTS study on two different SPAD layouts, implemented in 150 nm CMOS technology
Summary
The SPAD test chip we used contains two types of structures (Fig. 2): one layout is based on a P+/Nwell junction enclosed in a low-doped region, in order to create a guard-ring and avoid premature edge breakdown; a second layout includes a Pwell/Niso junction. In this case the generation rate is expressed by[32]: GBTBT ∼ AE5/2e−ξ0/E where E is the electric field, A a statistical factor temperature independent and ξ0 = 1.9 × 107Vcm−1 It should be noted the BTBT process shows a very weak dependence from temperature, due to the variation of silicon bandgap energy Eg with temperature[35]. In both cases, the activation energies are found to be lower than the silicon mid bandgap value, indicating that electric field enhancement mechanisms are involved in the physics of the DCR generation. P+/Nwell layout shows a lower activation energy with respect to Pwell/Niso layout: the higher doping concentrations and the smaller junction dimensions in P+/Nwell layout create a higher electric field in the multiplication r egion[29]
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