Abstract
The growing demands on compact and high-definition single-photon avalanche diode (SPAD) arrays have motivated researchers to explore pixel miniaturization techniques to achieve sub-10 μm pixels. The scaling of the SPAD pixel size has an impact on key performance metrics, and it is, thereby, critical to conduct a systematic analysis of the underlying tradeoffs in miniaturized SPADs. On the basis of the general assumptions and constraints for layout geometry, we performed an analytical formulation of the scaling laws for the key metrics, such as the fill factor (FF), photon detection probability (PDP), dark count rate (DCR), correlated noise, and power consumption. Numerical calculations for various parameter sets indicated that some of the metrics, such as the DCR and power consumption, were improved by pixel miniaturization, whereas other metrics, such as the FF and PDP, were degraded. Comparison of the theoretically estimated scaling trends with previously published experimental results suggests that the scaling law analysis is in good agreement with practical SPAD devices. Our scaling law analysis could provide a useful tool to conduct a detailed performance comparison between various process, device, and layout configurations, which is essential for pushing the limit of SPAD pixel miniaturization toward sub-2 μm-pitch SPADs.
Highlights
Single-photon avalanche diodes (SPADs) have been widely recognized for having unique features, such as single-photon sensitivity and picosecond timing resolution
Continuous efforts in single-photon avalanche diode (SPAD) research and development have led to the exponential growth of the array size and dramatic shrinkage of the pixel dimension; the SPAD array size has reached a milestone of 1 megapixel [1], while a SPAD pixel with 2.2 μm-pitch was reported in test devices [2]
Few attempts have been made to systematically analyze the impact of SPAD pixel scaling on major performance metrics, such as the fill factor (FF), photon detection probability (PDP), photon detection efficiency (PDE), dark count rate (DCR), correlated noise, and power consumption
Summary
Single-photon avalanche diodes (SPADs) have been widely recognized for having unique features, such as single-photon sensitivity and picosecond timing resolution. 3D-stacking approaches have enabled the physically isolation of pixel circuits from the SPAD array while ensuring electrical connection via pixel-level bonding, which provides a promising solution for pixel miniaturization below 10 μm [3,4,5,6] Such an aggressive miniaturization and scaling of SPAD pixels could have a major influence on the key performance of SPADs, and it is, thereby, critical for designers to understand the fundamental tradeoffs in miniaturized SPADs. Theoretical studies on SPAD performance have been widely performed based on both analytical methods and simulations to describe process, voltage, and temperature dependence [7,8,9].
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