High-Speed Active Quench and Reset Circuit for SPAD in a Standard 65 nm CMOS Technology

Abstract

A compact high-speed active quench and reset (AQR) circuit integrated with a p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /n-well single-photon avalanche diode (SPAD) is designed and fabricated in a standard 65 nm CMOS technology. The post-layout simulations showed that the quenching time for this AQR circuit is only 0.1 ns, and the smallest dead time is 3.35 ns which corresponds a maximum count rate of ~300 Mcps. The measurements showed that the SPAD pixel achieved a dark count rate of 21 kHz, a peak photon detection probability of 23.8% at a 420 nm wavelength and a timing jitter of 139 ps (using a 405 nm pulsed laser) when the excess voltage was 0.5 V. Also, due to the short quenching time, negligible afterpulsing was observed during the measurements.