Single-gate Devices Research Articles

Investigation of ft and fmax in Si and Si1–xGex based single and dual material double-gate Tunnel FETs for RF applications

This study optimizes Si1−xGex based double gate tunnel field effect transistor (TFET) for their high ON current (Ion) and lesser sub-threshold swing and compares Si and Si1−xGex based single material double gate (SMDG) and dual material double gate (DMDG) TFETs. This study also measures the two RF performance metrics, unity gain cut-off frequency (ft) and maximum oscillation frequency (fmax) by varying the structural parameters, gate length, gate oxide thickness, channel thickness and underlap. Compared to single material gate devices, dual material gate devices give higher Ion without compromising the leakage current for both Si and Si1−xGex based TFETs. Si1−xGex based TFETs offers higher ft and fmax compared to that of Si TFETs for all the structural parameter variations considered in this study. DMDG TFETs exhibit higher ft with respect to SMDG TFETs. SMDG TFETs offers more fmax compared to DMDG TFETs due to the smaller values of output conductance.

(Invited) Effects of Van Der Waals Interaction in 2D Layered Material FETs and Their Device Performance Benchmark

Most of the current electronic devices compose of millions of transistors that are packed into an area smaller than a fraction of a fingernail and the continuing improvement of consumer devices are driven by the miniaturization of these devices for the past four decades. By shrinking down the sizes of these electronic components, device performances are improved such as reducing power consumption and increasing device speed, as well as other enhancements such as complex functionalities, portability and cost reduction. This leads to the wide-spread usage of electronic devices in every aspect of society, from increasing productivity in automations in manufacturing industries to vital signs monitoring in biomedical sector. As the channel length of silicon transistors, the work horse of modern electronic devices, shrank from few hundred micrometres to tens of nanometres, new challenges had surfaced which necessitated the development of novel device designs and fabrication techniques, such as ultrathin body (UTB) technology, high-k gate dielectrics, strained channel material and tri-gate design in FinFET. While these advances in electronics have been instrumental in sustaining the Moore’s law for the past decade, further improvement in the coming years would require adoption of novel materials and transistor geometries. Since the successful demonstration of thermodynamically stable two dimensional (2D) graphene by Novoselov, et al. and Berger, et al. in 2004, and the subsequent studies on the properties of graphene and other layered 2D materials, the idea of using these atomically thin layers as the channel material in field-effect devices has been investigated extensively. A wide range of 2D materials have been proposed and studied, including graphene, transition metal dichalcogenides (TMDs), hexagonal boron nitride (h-BN) and black phosphorus (BP), as well as 2D version of traditional material such as silicene and germanene. Experimentally, most of these materials applied into FET type devices haven been demonstrated and theoretically, it has also been intensively studied their FET performance down to sub 10nm. However, the devices simulated thus far had been restricted to double gated structures, which have not been demonstrated experimentally. Furthermore, due to the weak van der Waal (vdW) forces between the 2D material layers, the electrostatic environment of single top gate device diverges from the usual ultra-thin materials. Therefore, in this work, using BP as the example, we firstly investigate the device performance of few-layer 2D layered material FETs with a single top gate device structure MOSFET and Schottky barrier FET. The current characteristics of the devices is obtained via a non-equilibrium Green’s function (NEGF) quantum simulator using Wannier function Hamiltonians based on first principle calculations, which enables the investigation of the individual BP layers potential profile at different gate biases. Therefore, the effect of van der Waals interlayer interaction on device performance and carrier transport properties in multilayer BP FETs can be fully and properly studied. Finally, we will discuss the ultimate voltage scalability of a double-gate ultra-thin body (DG-UTB) FETs employing materials from group IV, III-V, and 2-dimensional (2D) materials, including BP, MoS2, etc., based on International Technology Roadmap for Semiconductors (ITRS) projected specifications for high performance (HP) and low power (LP) technologies. The ballistic performance of FETs designed based on the ITRS specifications for 2018 and beyond was evaluated via the semiclassical ballistic transport model. The device performance of 2D layer materials in FET applications will be compared to devices based the conversional semiconductor materials, such as Si, Ge, InGaAs and GaSb, based on ITRS roadmap requirement and their potential applications fitted into the future needed will be also addressed to provide the guidelines for future industrial development.

DC Characteristics of AlGaN/GaN HEMTs Using a Dual-Gate Structure.

Multiple techniques such as fluoride-based plasma treatment, a p-GaN or p-AlGaN gate contact, and a recessed gate structure have been employed to modulate the threshold voltage of AlGaN/GaN-based high-electron-mobility transistors (HEMTs). In this study, we present dual-gate AlGaN/GaN HEMTs grown on a Si substrate, which effectively shift the threshold voltage in the positive direction. Experimental data show that the threshold voltage is shifted from -4.2 V in a conventional single-gate HEMT to -2.8 V in dual-gate HEMTs. It is evident that a second gate helps improve the threshold voltage by reducing the two-dimensional electron gas density in the channel. Furthermore, the maximum drain current, maximum transconductance, and breakdown voltage values of a single-gate device are not significantly different from those of a dual-gate device. For the fabricated single- and dual-gate devices, the values of the maximum drain current are 430 mA/mm and 428 mA/mm, respectively, whereas the values of the maximum transconductance are 83 mS/mm and 75 mS/mm, respectively.

P‐9: Improved Electrical Stability of Double‐Gate a‐IGZO TFTs

The electrical stability of double‐gate (DG) and single‐gate (SG) amorphous indium‐gallium‐zinc oxide (a‐IGZO) TFTs is investigated and compared. The SG device shows an abnormal negative shift in Vth accompanying with deterioration in SS under PBS, which is not observed in DG device or SG device stressed in vacuum. Moreover, the SG device exhibits a much larger negative Vth shift than DG device and SG device stressed in vacuum. The improved electrical stability of DG device comes from not only the lowered vertical electric field but also more effective moisture resistance due to the shield of DG electrodes.

Modeling the back gate effects of AlGaN/GaN HEMTs

This letter reports the design and simulation of novel AlGaN/GaN double-gate high electron mobility transistors (DG HEMTs) featuring enhanced back gate-control of the two dimensional electron gas in AlGaN/GaN heterostructures. A comparison study was carried out to reveal the difference between the performance of the AlGaN/GaN DG HEMTs and single-gate devices. The results show that the DG GaN-HEMTs can potentially offer a higher transconductance gain and better immunity of the short channel effects of drain induced barrier lowering and subthreshold swing than traditional single-gate HEMTs.

Light emissions from organic crystal field-effect transistors with dual-gate contacts

We incorporated a dual-gate structure into organic crystal field-effect transistors (OCFETs). An organic semiconductor crystal was laminated on the comb-shaped interdigitated Cr/Au source and drain that were preliminarily deposited on SiO2 (used as a bottom-gate insulator) covering Si (a bottom-gate contact). On top of the crystal, we successively formed a parylene top-gate insulator and an Au top-gate contact. High hole mobilities were observed by applying voltages to both gate contacts and by applying a certain voltage to the top-gate contact with the bottom-gate contact floated. The drain currents of dual-gate devices are larger than those of single-gate devices with only the bottom-gate contact. Dual-gate OCFETs produce light emissions with the application of alternating-current (AC) voltages to both gate contacts. The dual-gate OCFETs require gate voltages lower than those of single-gate devices. These results indicate that dual-gate structures are useful for realizing high hole mobilities and current-injected light emissions by facilitating carrier injections into the OCFETs.

Bulk Accumulation a-IGZO TFT for High Current and Turn-On Voltage Uniformity

We present here an amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) in which the accumulation layer is not only confined to the a-IGZO/gate-insulator interface, but extends the entire depth of the a-IGZO. This bulk accumulation TFT is achieved by the use of top- and bottom-gate, that are electrically tied together, resulting in drain current that is over seven times higher than that of a single-gate device, for an a-IGZO thickness of 10 nm. Thus, high drive current is achieved for a relatively small channel width due to bulk accumulation. Furthermore, being independent of carrier scattering at the interface and owing to the bulk accumulation/depletion, the subthreshold swing is always small and turn-on voltage around zero volts with device-to-device uniformity that is much better than that of single-gate TFTs.

Solution-Processed Dual-Gate Polymer Field-Effect Transistors for Display Applications

We describe the advantages of dual-gate thin-film transistors (TFTs) for display applications. We show that in TFTs with active semiconductor layers composed of diketopyrrolopyrrole-naphthalene copolymer, the on-current is increased, the off-current is reduced, and the sub-threshold swing is improved compared to single-gate devices. Charge transport measurements in steady-state and under non-quasi-static conditions reveal the reasons for this improved performance. We show that in dual-gate devices, a much smaller fraction of charge carriers move in slow trap states. We also compare the activation energies for charge transport in the top-gate and bottom-gate configurations.

Multiband tunneling in trilayer graphene

The electronic tunneling properties of the two stable forms of trilayer graphene (TLG), rhombohedral ABC and Bernal ABA, are examined for pn and pnp junctions as realized by using a single gate (SG) or a double gate (DG). For the rhombohedral form, due to the chirality of the electrons, the Klein paradox is found at normal incidence for SG devices while at high energy interband scattering between additional propagation modes can occur. The electrons in Bernal ABA TLG can have a monolayer- or bilayer-like character when incident on a SG device. Using a DG however both propagation modes will couple by breaking the mirror symmetry of the system which induces intermode scattering and resonances that depend on the width of the DG pnp junction. For ABC TLG the DG opens up a band gap which suppresses Klein tunneling. The DG induces also an unexpected asymmetry in the tunneling angle for single valley electrons.

Pinch-Off Effect in P-Type Double Gate and Single Gate Junctionless Silicon Nanowire Transistor Fabricated by Atomic Force Microscopy Nanolithography

The spark of aggressive scaling of transistors was started after the Moors law on prediction of device dimensions. Recently, among the several types of transistors, junctionless transistors were considered as one of the promising alternative for new generation of nanotransistors. In this work, we investigate the pinch-offeffect in double gate and single gate junctionless lateral gate transistors. The transistors are fabricated on lightly doped (1015) p-type Silicon-on-insulator wafer by using an atomic force microscopy nanolithography technique. The transistors are normallyonstate devices and working in depletion mode. The behavior of the devices confirms the normal behavior of the junctionless transistors. The pinch-offeffect appears at VG+2.0 V and VG+2.5 V for fabricated double gate and single structure, respectively.Onstate current is in the order of 10-9(A) for both structures due to low doping concentration. The single gate and double gate devices exhibit anIon/Ioffof approximately 105and 106, respectively.

3D modeling of dual-gate FinFET

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at Vg1 >Vg2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.

Comparison of Electrical Properties and Bias Stability of Double-Gate a-HIZO TFTs According to TFT Structure

We fabricated two types of double-gate amorphous hafnium-indium-zinc oxide thin-film transistors: a back-channel etch (BCE) type and an etch stopper (ES) type. The normalized on-current and field-effect mobility of the BCE type are larger than those of the ES type. Furthermore, when applied with a positive bias stress, stability trends compared for each single-gate device are different according to structures. We suggest that the reason for the different electrical properties and bias stability originates from the ES structure in which some regions under the source/drain electrodes block the top-gate field; thus, there is no carrier accumulation or charge trapping into the dielectric layer.

Single‐Gate Bandgap Opening of Bilayer Graphene by Dual Molecular Doping

Dual doping-driven perpendicular electric field with opposite directions remarkably increase the on/off current ratio of bilayer graphene field-effect transistors. This unambiguously proves that it is possible to open a bandgap with two molecular dopants (F4-TCNQ and NH2 -functionalized self-assembled monolayers (SAMs)) even in a single-gate device structure.

Device architectures for improved amorphous polymer semiconductor thin-film transistors

In this letter, the performance characteristics of single-gate and dual-gate thin-film transistors (TFTs) with amorphous indenofluorene–phenanthrene copolymer semiconductor active layers are reported. Optimized single-gate devices possess mobilities up to 0.15 cm 2/V-s and width-normalized contact resistance of 1275 Ωcm. These results were obtained through the combination of a recessed source/drain structure and suitable surface treatments of source/drain contact electrodes. The characteristics of dual-gate indenofluorene–phenanthrene copolymer TFTs with polymer gate insulators are also reported. This structure exhibits increased on-current, reduced threshold voltage, improved sub-threshold swing and increased on–off current ratio compared to single-gate architectures.

Performance Comparison of Single- and Dual-Gate Carbon-Nanotube Thin-Film Field-Effect Transistors

In this paper, we present the performance comparison of a planar dual-gate semiconducting-nanotube thin-film transistor (SNTFT) with single-gate SNTFTs. A thin film of 95% enriched semiconducting single-walled carbon nanotubes (SWCNTs) is deposited on the amino-silane-modified hafnium oxide (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> ) surface. HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> deposited by radio-frequency sputtering is used as the dielectric material for the back gate of the SNTFT, and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> is used as the dielectric material for the top gate. The performance of SNTFTs with the gate structures located at the top, bottom, or both the top and the bottom (dual gate) of the SWCNT thin-film channel is compared. All SNTFTs have exhibited a p-type output characteristic behavior with distinct saturation and a linear region of operation. The electrical characterization of these devices shows that the dual-gate SNTFT out performs the single-gate devices in terms of subthreshold slopes, threshold voltage, and on-off current ratios. The dual-gate SNTFT exhibits a subthreshold slope of 280 mV/dec, a threshold voltage of -0.65 V, and a maximum on-off drain current ratio of 1.2 × 103. A maximum transconductance value of 5.89 μS and a charge carrier mobility value of 2.26 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s obtained for the dual-gate SNTFT are greater compared with the corresponding values of single-gate SNTFTs having identical dimensions.

High mobility top-gate and dual-gate polymer thin-film transistors based on diketopyrrolopyrrole-naphthalene copolymer

In this letter, the performance characteristics of top-gate and dual-gate thin-film transistors (TFTs) with active semiconductor layers consisting of diketopyrrolopyrrole-naphthalene copolymer are described. Optimized top-gate TFTs possess mobilities of up to 1 cm2/V s with low contact resistance and reduced hysteresis in air. Dual-gate devices possess higher drive currents as well as improved subthreshold and above threshold characteristics compared to single-gate devices. We also describe the reasons that dual-gate devices result in improved performance. The good stability of this polymer combined with their promising electrical properties make this material a very promising semiconductor for printable electronics.

Nanosecond pulsed field emission from single-gate metallic field emitter arrays fabricated by molding

Electrically gated pulsed field emission from molybdenum field emitter arrays was studied. Single-gate field emitter array devices supported by metallic substrates were fabricated by a combination of molding and a self-aligned gate process. Devices were tested in a low-inductance cathode holder compatible with the high-acceleration electric field of a pulsed diode gun. Pulsed field emission down to 1.1 ns was observed for single-gate devices with 1.2×103–1.2×105 emitter tips with 5 μm array pitches. Integrating the field emitter arrays in a high-voltage pulsed diode gun, the authors demonstrated nanosecond field emission at an acceleration field of 30 MV/m at the cathode surface and acceleration of the field emission electron beam up to 300 keV. In addition, transverse beam emittance of the single-gate devices was measured with two different array sizes.

Equivalent Oxide Thickness of Trigate SOI MOSFETs With High-$\kappa$ Insulators

The evolution of traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) from planar single-gate devices into 3-D ones with multiple gates and high-kappa insulators imposes the use of new electrical models that accurately reproduce their behavior. This paper demonstrates that the typical expression of equivalent oxide thickness (EOT) for planar devices with high- kappa gate insulators becomes useless for nonplanar ones such as triple-gate (trigate) silicon-on-insulator MOSFETs. An alternative expression of the EOT for these trigate devices has been developed through a semianalytical approach to the gate-insulator capacitance. The proposed model correctly reproduces the total electron density in a wide range of device dimensions and applied biases.

Monte Carlo simulation of nanoelectronic devices

The Monte Carlo simulation method is used to analyze the behavior of electron and hole mobility in different nanoelectronic devices including double gate transistors and FinFETs. The impact of technological parameters on carrier mobility is broadly discussed, and its behavior physically explained. Our main goal is to show how mobility in multiple gate devices compares to that in single gate devices and to study different approaches to improve the performance of these devices. Simulations of ultrashort channel devices taking into account quantum effects are also shown.

Fabrication of all-metal field emitter arrays with controlled apex sizes by molding

The authors proposed a method to fabricate field emitter arrays with uniform apex diameters in tens of nanometer scale based on the molding technique and apply it to fabricate molybdenum field emitter arrays. Apex diameter equal to 23±5nm was observed in a 6×6 tip array by high-resolution scanning electron microscope. They also studied the field-emission characteristics in devices with gate electrodes fabricated on top of the arrays by a self-aligned process. In single-gate devices, emission current of up to 20μA per tip with negligible gate leak current was observed. The gate-fabrication process was extended to fabricate double-gated emitters. Further optimization of the fabrication process for higher emission current, together with metallurgical and lithographic methods, is discussed.