Abstract
The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at Vg1 >Vg2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.
Highlights
Accuracy of modeling of any semiconductor device is an issue of the production cost at its onset
In recent years we studied the performance of metal semiconductor field-effect transistors (MESFETs) and high electron mobility transistors (HEMTs) manufactured by semiconductor companies, where the design was based on our novel concept of tailoring the electrical field along a channel of FETs
Comparing electrical field profiles at the top of the channel obtained from 3D models for finshaped field-effect transistors (FinFETs) with (Figure 2a) and without the top segment (Figure 2b) of the gate, we observed the following: 1. Wrapped gate creates a stronger field at the top than the field at the top of the FinFET without the horizontal gate segment
Summary
Accuracy of modeling of any semiconductor device is an issue of the production cost at its onset. The widely used commercial package of semiconductor device design named Silvaco offers 2D and 3D modeling options along with quantization effects. The 2D modeling is the main design tool. We selected a very simple way to judge our results by modeling an existing FinFET which was produced not by our group but by researchers at UC Berkley [1]. Their FinFET was tested after fabrication, and we compared our modeling results with the actual performance characteristics of the transistor
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