Single Event Transient Pulse Width Research Articles

A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs)

Radiation-induced single event transients (SETs) are expected to evolve to single event multiple transients (SEMTs) due to the downscaling of transistor feature size, which also increases the difficulty of the vulnerability estimation for large-scale digital integrated circuits. In this paper, a novel layout-based soft error vulnerability estimation approach which is termed LBSEVEA is proposed to evaluate the impact of heavy ions on the vulnerability of combinational circuits. The physical process of interaction between particles and devices, especially nuclear reaction and scattering process are included in the LBSEVEA. In addition, ambipolar diffusion and bipolar amplification effect, which induce additional charge collection of the adjacent transistors and the hitting transistor, are also considered. A new method calculating the collected charge induced by the bipolar amplification effect is presented. By introducing the layout information of the target circuits into the identification of the adjacent cells, SEMTs effect can be considered in the vulnerability estimation. A fast SPICE simulation tool is adopted to conduct the fault injected netlist simulations, which can make a favorable compromise between the consumption of computer resources and simulation precision. Furthermore, induced soft error numbers, distributions of charge collected by the hitting nodes and the adjacent nodes, and SET pulse width distributions are presented. Besides, heatmaps of induced pulse widths for the layout of two benchmark circuits are provided. Finally, the constraints, the flexibility, and the scalability of the LBSEVEA are discussed. The ability to estimate the impact of process variations on the vulnerability is also presented. Compared with simulation and experimental results, the LBSEVEA can fairly estimate the vulnerability of combinational circuits.

Exploiting SEU Data Analysis to Extract Fast SET Pulses

A method is presented to enhance single-event transient (SET) measurements by overcoming a common experimental limitation of minimum measurable pulse widths. As technology scales, SETs decrease in width and measurement circuits fundamentally cannot capture every fast transient capable of causing an error. A method has been developed to overcome this limitation by using a latch as a feedback-assisted fast transient capture circuit. Single-event upset (SEU) data are combined with SET data to extend pulsewidth acuity such that pulses faster than the minimum measurable SET pulsewidth are extracted. The method has been applied for a 14-/16-nm bulk FinFET technology node and predictions for logic single-event cross section reveal the impact of fast transients on the radiation response of logic circuits. Results including the extracted fast transients represent upper bound SEU cross sections. For high linear energy transfer (LET) particle irradiation, accounting for fast transients using the developed method results in negligible variation in logic SE cross section. However, for low LET particle irradiation, the method results in an order of magnitude increase in logic SE cross section.

The Effect of Deep N+ Well on Single-Event Transient in 65 nm Triple-Well NMOSFET

In a triple-well NMOSFET, a deep n+ well (DNW) is buried in the substrate to isolate the substrate noise. The presence of this deep n+ well leads to changes in single-event transient effects compared to bulk NMOSFET. In space, a single cosmic particle can deposit enough charge in the sensitive volume of a semiconductor device to cause a potential change in the transient state, that is, a single-event transient (SET). In this study, a quantitative characterization of the effect of a DNW on a SET in a 65 nm triple-well NMOSFET was performed using heavy ion experiments. Compared with a bulk NMOSFET, the experimental data show that the percentages of average increase of a SET pulse width are 22% (at linear energy transfer (LET) = 37.4 MeV·cm2/mg) and 23% (at LET = 22.2 MeV·cm2/mg) in a triple-well NMOSFET. This study indicates that a triple-well NMOSFET is more sensitive to a SET, which means that it may not be appropriate for radiation hardened integrated circuit design compared with a bulk NMOSFET.

Single Event Transient Study of pMOS Transistors in 65 nm Technology With and Without a Deep n+ Well Under Particle Striking

In triple-well PMOSFET transistor, a deep n+ well (DNW) is a process used to isolate the substrate noise, which can lead to changes in effect of single event transient (SET). In outer space, collision of cosmic energetic particles with sensitive nodes of integrated circuits can generate electron-hole pairs. The probability of recombination of electrons and holes is different, which results in transient changes of sensitive nodes’ state. Transient potential change is transmitted to the output terminal, that is, a single event transient. In this paper, measured SET effect characteristics of PMOSFET transistors in 65 nm process are performed with heavy particle experiments. Compared with triple-well PMOSFET transistor, the experimental data show that the average of SET pulse width in double-well PMOSFET is increased by 19.4% (Ge linear energy transfer (LET) = 37.4 MeV $\cdot $ cm2/mg) and 14.4% (Ti LET = 22.2 MeV $\cdot $ cm2/mg). The data show that a triple-well PMOSFET transistor is better for SET, which is be appropriate for radiation hardened integrated circuits (ICs) design.

Effect of Transistor Variants on Single-Event Transients at the 14-/16-nm Bulk FinFET Technology Generation

Single-event transient (SET) data for the 14-/16-nm bulk finFET technology generation are presented and analyzed for variations in threshold voltage and number of fins in the transistor. The heavy-ion experimental data over a range of supply voltage allows for a comparison of the impact of drive current on the SET response of each transistor variant. The results show that the transistor drive current is a key factor for determining SET pulsewidths and cross sections for high linear energy transfer particle irradiation. Transistor variant data that result in matching transistor drive current show an excellent match for SET pulsewidths and cross sections.

Study of the operation and SET robustness of a CMOS pulse stretching circuit

This paper analyzes the normal response and the sensitivity to Single Event Transients (SETs) of a CMOS pulse stretching circuit used for the SET pulse width measurement. The pulse stretcher based on two cascaded asymmetrically sized inverters, designed in IHP's 130 and 250nm bulk CMOS technologies, has been studied. Results from SPICE simulations have confirmed that both the normal response (pulse stretching) and the SET robustness (critical charge) of the pulse stretcher are dominantly influenced by the PMOS-to-NMOS sizing ratio. In addition, the operation and SET robustness of the pulse stretcher are influenced by the load, operating temperature, supply voltage variations, process corners and parasitic capacitances of interconnections. The typical process-induced mismatch in transistors' sizes is not a critical issue in this case. It was demonstrated that the multi-stage pulse stretching configuration is more suitable for obtaining wider pulses, but on the other hand is more susceptible to SETs than the single-stage (two-inverter) pulse stretcher. Based on the acquired results, a general approach for the design of a CMOS pulse stretcher, taking into consideration the impact of all analyzed parameters on its normal response and SET robustness, has been proposed.

The Impact of Charge Collection Volume and Parasitic Capacitance on SEUs in SOI- and Bulk-FinFET D Flip-Flops

Measured single-event (SE) heavy-ion data for comparable silicon on insulator (SOI) and bulk silicon FinFET D flip-flop (DFF) designs demonstrate a notably greater difference between the SOI and bulk responses, which has commonly been observed. Data show greater than $30\times $ in SE upset (SEU) LET threshold and 3 orders of magnitude decrease in saturated SE cross section for SOI FinFETs when compared to bulk FinFETs. The difference in SEU threshold is shown to be due to the saturation of SE transient (SET) pulsewidths at values that are comparable to feedback-loop delays of DFF design in the SOI technology. The feedback-loop delays in FinFET technologies are significantly impacted by the inherent parasitic capacitance. For the bulk technology, SET pulsewidths do not saturate due to charge collection from the substrate region.

Impact of Single-Event Transient Duration and Electrical Delay at Reduced Supply Voltages on SET Mitigation Techniques

Single-event transients (SETs) in 16-/14-nm bulk fin field effect transistor (finFET) logic chains have been measured using a custom-designed test IC. A variety of logic gate chains were designed, and SET pulse widths were obtained across a wide range of supply voltages. In light of the increased SET response at reduced supply voltages, the efficacy of filter-based mitigation is assessed by analyzing the voltage dependence of SET duration against the characteristic electrical inverter delay.

NMOS Transistor Location Adjustment for N-Hit Single-Event Transient Mitigation in 65-nm CMOS Bulk Technology

Heavy-ion experiments demonstrated that reducing the distance between nMOS transistor and n-well can reduce N-hit (i.e., hit nMOS transistor) single-event transient (SET) pulsewidth. This principle can be applied for radiation-harden-by-design standard cell design without any area overhead. TCAD simulations indicated that the guard drain effect of the n-well and the enhanced restore current of pMOS transistor are responsible for the N-hit SET pulsewidth reduction.

Evidence of Pulse Quenching in AND and OR Gates by Experimental Probing of Full Single-Event Transient Waveforms

We present experimental results obtained from full-waveform measurements of single-event transients (SETs) occurring in the conventional two-input AND and OR gates under focused heavy-ion radiation. Chips with test circuits were fabricated in a 65-nm bulk CMOS technology, and were irradiated in a microbeam facility using 197Au and 48Ca species. The resulting SETs were sensed using a dedicated on-chip analog multiplexer circuit. The obtained position-dependent ion hit responses were analyzed, and the strong evidence of charge-sharing-induced pulse quenching was observed. For SETs that propagated through the inverting stage of AND and OR circuits, a significant degradation of measured SET pulse widths and heights was seen. These observations are in good accordance with earlier published simulation and experimental results based on inverter chains. Test circuits also exhibited distinct SET responses depending on their logic state, making the AND gate a better candidate for exploiting the pulse quenching effect when circuits are placed in a triple well.

Improved on-chip self-triggered single-event transient measurement circuit design and applications

Single-event transient (SET) induced soft errors are becoming more and more a threat to the reliability of electronic systems in space. The SET pulse width is an important parameter characterizing the possibility of an SET being latched by a sequential element such as a flip-flop. This paper improves the widely used on-chip self-triggered SET measurement circuit by changing it from a single SET measurement module to a combination of two modules. One module is responsible for measuring narrow SET pulse widths while the other is responsible for measuring modest and wide SET pulse widths. In this way, the range of measurable SET pulse width is increased. Pulsed laser facility is used to simulate single-event transients induced by single-particles. Experimental results demonstrate that the minimum accurately measured SET pulse width is decreased from 166.5ps to 33.3ps after adopting the proposed design when compared with the original one. SET pulse width broadening effect was also observed using the measurement system. The broadening factor was measured to be 0.123–0.143ps/inverter.

Characterization of Single-Event Transients in Schmitt Trigger Inverter Chains Operating at Subthreshold Voltages

Single-event transients (SETs) induced by alpha particles and heavy ions are measured and analyzed with subthreshold voltage SET characterization circuits. Using a Schmitt trigger inverter target chain fabricated in a 65-nm bulk CMOS process, SET pulse widths are captured from an operating voltage down to 0.32 V. At nominal voltages, the Schmitt trigger inverter chain is immune to SETs, but at subthreshold voltages energetic particles can induce SET pulse widths that range up to and over a microsecond. Additionally, the results show that at subthreshold voltages the 28-nm node offers a significant improvement in the SET response over the 65-nm node.

Estimating Single-Event Logic Cross Sections in Advanced Technologies

Reliable estimation of logic single-event upset (SEU) cross section is becoming increasingly important for predicting the overall soft error rate. As technology scales and single-event transient (SET) pulse widths shrink to widths on the order of the setup-and-hold time of flip-flops, the probability of latching an SET as an SEU must be reevaluated. In this paper, previous assumptions about the relationship of SET pulsewidth to the probability of latching an SET are reconsidered and a model for transient latching probability has been developed for advanced technologies. A method using the improved transient latching probability and SET data is used to predict logic SEU cross section. The presented model has been used to estimate combinational logic SEU cross sections in 32-nm partially depleted silicon-on-insulator (SOI) technology given experimental heavy-ion SET data. Experimental SEU data show good agreement with the model presented in this paper.

A Novel Layout-Based Single Event Transient Injection Approach to Evaluate the Soft Error Rate of Large Combinational Circuits in Complimentary Metal-Oxide-Semiconductor Bulk Technology

As the technology scales down, space radiation induced soft errors are becoming a critical issue for the reliability of Integrated Circuits (ICs). In this paper, we propose a novel layout-based Single-Event Transient (SET) injection approach to evaluate the Soft Error Rate (SER) of large combinational circuits in Complementary Metal-Oxide-Semiconductor (CMOS) bulk technology. We consider the effect of ion strike location on the SET pulse width in this approach. Heavy-ion experiments on two different inverter chains are conducted to verify this layout-based SET injection approach. The simulation and experiment results show that this approach can fairly reflect the SET pulse width distribution. Furthermore, we compare the soft error number calculated by our proposed layout-based approach with the normal SET injection approach, and illustrate the detailed circuit response obtained by our proposed approach.

Effect of supply voltage and body-biasing on single-event transient pulse quenching in bulk fin field-effect-transistor process**Project supported by the National Natural Science Foundation of China (Grant Nos. 61376109, 61434007, and 61176030).

Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor (FinFET) technology. However, the studies of charge sharing induced single-event transient (SET) pulse quenching with bulk FinFET are reported seldomly. Using three-dimensional technology computer aided design (3DTCAD) mixed-mode simulations, the effects of supply voltage and body-biasing on SET pulse quenching are investigated for the first time in bulk FinFET process. Research results indicate that due to an enhanced charge sharing effect, the propagating SET pulse width decreases with reducing supply voltage. Moreover, compared with reverse body-biasing (RBB), the circuit with forward body-biasing (FBB) is vulnerable to charge sharing and can effectively mitigate the propagating SET pulse width up to 53% at least. This can provide guidance for radiation-hardened bulk FinFET technology especially in low power and high performance applications.

A Comparison of the SEU Response of Planar and FinFET D Flip-Flops at Advanced Technology Nodes

Heavy-ion experimental results were used to characterize single-event upset trends in 16 nm bulk FinFET, 20 nm bulk planar, and 28 nm bulk planar D flip-flops. Experimental data show that 16 nm bulk FinFET flip-flops have considerably lower SEU cross sections than their sub-32 nm planar counterparts for linear energy transfer (LET) less than $10~\hbox{MeV-{cm}}^{2}/\hbox{mg}$ . However, FinFET SEU cross section improvement compared to the planar technologies is weak for high LET particles. Three-dimensional technology computer-aided design simulations are used to investigate charge collection mechanisms and single-event transient (SET) pulse widths at these advanced fabrication nodes. Simulation results show that SETs follow conventional scaling trends, which are that SET pulse widths reduce with technology scaling.

Simulation Study of Node-State Transition Effect on the Single-Event Transient

Using 3-D technology computer-aided design numerical simulation, we comprehensively analyze the impact of node-state transition on a single-event transient (SET) pulse. Simulation results present that the SET pulsewidth is a function of the node current state and the state transition time. Based on the simulation results, we quantize the difference between the static SET injection and the dynamic SET injection.

Radiation hardness evaluations of 65 nm fully depleted silicon on insulator and bulk processes by measuring single event transient pulse widths and single event upset rates

We measure single event transient (SET) pulse widths on inverter chains and single event upset (SEU) rates on flip-flops (FFs) fabricated in 65 nm fully depleted silicon on insulator (FD-SOI) and bulk processes. The layout designs of test chips are strictly identical between their processes besides buried oxide (BOX) layers. Experimental results show that neutron-induced SEU and SET rates in the FD-SOI process are 230× and 450× lower than those in the bulk process, respectively.

Single event transients in a 0.18 m partially-depleted silicon-on-insulator complementary metal oxide semiconductor circuit

Single event transients (SETs) in a 100 series 0.18 m partially- depleted silicon-on-insulator (PDSOI) complementary metal oxide semiconductor (CMOS) inverter chain are studied by using pulsed laser. In this paper, effects of struck transistor type and struck locations on the threshold laser energy and the pulse width of SETs are investigated. Results show that the threshold laser energies at different locations are similar, but the threshold laser energies of n-channel metal-oxide-semiconductor (NMOS) transistors are much smaller than that of p-channel metal-oxide-semiconductor (PMOS) transistors. The SET pulse width of n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) is 427.5 ps as measured at the output terminal when the 2nd stage is irradiated, and 287.4 ps when the 100th stage is irradiated; the SET pulse width of p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) is 295.9 ps as measured at the output terminal when the 1st stage is irradiated, and 150.5 ps when the 99th stage is irradiated. Both broadening rates are about 1.4 ps/stage. When the struck locations are close to the output terminal of the chain, the SET pulse is narrowed; however, when the struck nodes are close to the input terminal, the SET pulse is broadened. SET pulses are progressively broadened up when propagating is along inverter chains. A similar broadening rate in neither NMOSFET nor PMOSFET, indicates that the SET pulse broadening effect is caused by propagation, independent of the type of struck transistors. Through analysis, the charge of floating body-induced threshold voltage hysteresis in PDSOI transistors is the main cause of pulse broadening. The positive SET pulse observed on the oscilloscope, contrary to the expectation, is due to charging and discharging of the output node capacitor. Also, the observed sub-rail-to-rail swings of the SET pulses are due to the voltage division between the internal resistance of the oscilloscope and the resistance of the PMOS transistor.

Effects of drain-wall in mitigating N-hit single event transient via 45 nm CMOS process

A three-dimensional (3D) technology computer-aided design (TCAD) simulation in a novel layout technique for N-hit single event transient (SET) mitigation based on drain-wall layout technique is proposed. Numerical simulations of both single-device and mixed-mode show that the proposed layout technique designed with 45 nm CMOS process can efficiently reduce not only charge collection but also SET pulse widths (WSET). What is more, simulations show that impacts caused by part of ion-incidents can be shielded with this novel layout technique. When compared with conventional layout technique and guard drain layout technique, we find that the proposed novel layout technique can provide the best benefit of SET mitigation with a small sacrifice in effective area.