NMOS Transistor Location Adjustment for N-Hit Single-Event Transient Mitigation in 65-nm CMOS Bulk Technology

Abstract

Heavy-ion experiments demonstrated that reducing the distance between nMOS transistor and n-well can reduce N-hit (i.e., hit nMOS transistor) single-event transient (SET) pulsewidth. This principle can be applied for radiation-harden-by-design standard cell design without any area overhead. TCAD simulations indicated that the guard drain effect of the n-well and the enhanced restore current of pMOS transistor are responsible for the N-hit SET pulsewidth reduction.