Abstract
As the technology scales down, space radiation induced soft errors are becoming a critical issue for the reliability of Integrated Circuits (ICs). In this paper, we propose a novel layout-based Single-Event Transient (SET) injection approach to evaluate the Soft Error Rate (SER) of large combinational circuits in Complementary Metal-Oxide-Semiconductor (CMOS) bulk technology. We consider the effect of ion strike location on the SET pulse width in this approach. Heavy-ion experiments on two different inverter chains are conducted to verify this layout-based SET injection approach. The simulation and experiment results show that this approach can fairly reflect the SET pulse width distribution. Furthermore, we compare the soft error number calculated by our proposed layout-based approach with the normal SET injection approach, and illustrate the detailed circuit response obtained by our proposed approach.
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