Effects of drain-wall in mitigating N-hit single event transient via 45 nm CMOS process

Abstract

A three-dimensional (3D) technology computer-aided design (TCAD) simulation in a novel layout technique for N-hit single event transient (SET) mitigation based on drain-wall layout technique is proposed. Numerical simulations of both single-device and mixed-mode show that the proposed layout technique designed with 45 nm CMOS process can efficiently reduce not only charge collection but also SET pulse widths (WSET). What is more, simulations show that impacts caused by part of ion-incidents can be shielded with this novel layout technique. When compared with conventional layout technique and guard drain layout technique, we find that the proposed novel layout technique can provide the best benefit of SET mitigation with a small sacrifice in effective area.