Silicon Nanowire Field-effect Transistors Research Articles

Effect of Gamma Irradiation on Dynamics of Charge Exchange Processes between Single Trap and Nanowire Channel.

In the present study, transport properties and single trap phenomena in silicon nanowire (NW) field-effect transistors (FETs) are reported. The dynamic behavior of drain current in NW FETs studied before and after gamma radiation treatment deviates from the predictions of the Shockley-Read-Hall model and is explained by the concept taking into account an additional energy barrier in the accumulation regime. It is revealed that dynamics of charge exchange processes between single trap and nanowire channel strongly depend on gamma radiation treatment. The results represent potential for utilizing single trap phenomena in a number of advanced devices.

An innovative large scale integration of silicon nanowire-based field effect transistors

Since the early 2000s, silicon nanowire field effect transistors are emerging as ultrasensitive biosensors while offering label-free, portable and rapid detection. Nevertheless, their large scale production remains an ongoing challenge due to time consuming, complex and costly technology. In order to bypass these issues, we report here on the first integration of silicon nanowire networks, called nanonet, into long channel field effect transistors using standard microelectronic process. A special attention is paid to the silicidation of the contacts which involved a large number of SiNWs. The electrical characteristics of these FETs constituted by randomly oriented silicon nanowires are also studied. Compatible integration on the back-end of CMOS readout and promising electrical performances open new opportunities for sensing applications.

Performance and Variability Analysis of SiNW 6T-SRAM Cell Using Compact Model With Parasitics

In this paper, we analyze stability metrics [e.g., read, write noise margins (WNM), and access time], geometrical variability, and layout area optimization of silicon nanowire field effect transistor (SiNW FET) based 6T SRAM with multiwire sizing technique. The SRAM cell analyzed in this paper is based on the TCAD and experimentally verified SiNW FET Verilog-A compact model with parasitics. The different NW SRAM design configurations (e.g., $\boldsymbol{C}\_111$ , $\boldsymbol{C}\_123$ , etc., ${{\mathbf where}}\,\boldsymbol{C}\_111$ denotes the number of wires in pull-up, access, and pull-down transistors, respectively) are investigated. The read static noise margin and read access time (RAT) are improved up to ∼38% and ∼18% with little pay of WNM by ∼9% (↓), write access time (WAT) ∼33% (↑) in $\boldsymbol{C}\_112$ configuration compared to $\boldsymbol{C}\_111$ . Other configuration such as $\boldsymbol{C}\_113$ possess more improvements upto ∼55%, ∼20% in RNM, RAT with WNM (↓∼21%), and WAT (∼44%↑) compare to $\boldsymbol{C}\_111$ at the expense of more layout area. Finally, the impact of geometrical variability including length, radius, and oxide thickness on the read and write stability using N -curve is examined. It is found that the static read and write stability is less susceptible to variability at nominal supply voltage. However, it is very sensitive to the voltage scaling in which read (write) voltage margin varies upto ∼2–3% (∼2.5–4.5%) and read (write) current margin varies upto ∼18% (∼35%) depending upon the design configurations. Among all design configurations, $\boldsymbol{C}\_112$ is the better configuration for considering overall performances such as write stability, speed, layout area, and variability tolerance.

Nanoelectronic Platform for Ultrasensitive Detection of Protein Biomarkers in Serum using DNA Amplification

Silicon nanowire field effect transistors (NWFETs) are low noise, low power, ultrasensitive biosensors that are highly amenable to integration. However, using NWFETs to achieve direct protein detection in physiological buffers such as blood serum remains difficult due to Debye screening, nonspecific binding, and stringent functionalization requirements. In this work, we performed an indirect sandwich immunoassay in serum combined with exponential DNA amplification and pH measurement by ultrasensitive NWFET sensors. Measurements of model cytokine interleukin-2 concentrations from <20 fM to >200 pM were demonstrated, surpassing the conventional NWFET urease-based readout. Our approach paves way for future development of universal, highly sensitive, miniaturized, and integrated nanoelectronic devices that can be applied to a wide variety of analytes.

The application of silicon nanowires field-effect transistor biosensor in medicine

Ultra-sensitive and quantitative analysis of proteins, nucleic acid, virus and other biochemical species are critical technologies for effective dianosis of disease, as well as medical studies. Silicon nanowires field-effect transistor (SiNWs-FET) biosensor is one of the most promising powerful platforms for label-free, real-time, ultra-sensitive detection of analyte. Here, the working principle of SiNWs-FET biosensor and the applications of SiNWs-FET biosensors in medicine were introduced. Moreover, the methods for enhancing the sensitivity of SiNWs-FET biosensor were discussed. Lastly, the prospecting of SiNWs-FET biosensor was presented.

System-Level Sensitivity Analysis of SiNW-bioFET-Based Biosensing Using Lock-In Amplification

Although silicon nanowire biological field-effect transistors (SiNW-bioFETs) have steadily demonstrated their ability to detect biological markers at ultra-low concentration, they have not yet translated into routine diagnostics applications. One of the challenges inherent to the technology is that it requires an instrumentation capable of recovering ultra-low signal variations from sensors usually designed and operated in a highly resistive configuration. Often overlooked, the SiNW-bioFET/instrument interactions are yet critical factors in determining overall system biodetection performances. Here, we carry out, for the first time, the system-level sensitivity analysis of a generic SiNW-bioFET model coupled to a custom-design instrument based on the lock-in amplifier. By investigating a large parametric space spanning over both sensor and instrumentation specifications, we demonstrate that system-wide investigations can be instrumental in identifying the design trade-offs that will ensure the lowest limits of detection. The generic character of our analytical model allows us to elaborate on the most general SiNW-bioFET/instrument interactions and their overall implications on detection performances. Our model can be adapted to better match specific sensor or instrument designs to either ensure that ultra-high sensitivity SiNW-bioFETs are coupled with an appropriately sensitive and noise-rejecting instrumentation, or to best tailor SiNW-bioFET design to the specifications of an existing instrument.

Memory characteristics of silicon nanowire transistors generated by weak impact ionization

In this study, we demonstrate the static random access memory (SRAM) characteristics generated by weak impact ionization in bendable field-effect transistors (FETs) with n+-p-n+ silicon nanowire (SiNW) channels. Our bendable SiNW FETs show not only superior switching characteristics such as an on/off current ratio of ~105 and steep subthreshold swing (~5 mV/dec) but also reliable SRAM characteristics. The SRAM characteristics originate from the positive feedback loops in the SiNW FETs generated by weak impact ionization. This paper describes in detail the operating mechanism of our device and demonstrates the potential of bendable SiNW FETs for future SRAM applications.

Logic Locking Using Hybrid CMOS and Emerging SiNW FETs

The outsourcing of integrated circuit (IC) fabrication services to overseas manufacturing foundry has raised security and privacy concerns with regard to intellectual property (IP) protection as well as the integrity maintenance of the fabricated chips. One way to protect ICs from malicious attacks is to encrypt and obfuscate the IP design by incorporating additional key gates, namely logic encryption or logic locking. The state-of-the-art logic encryption techniques certainly incur considerable performance overhead upon the genuine IP design. The focus of this paper is to leverage the unique property of emerging transistor technology on reducing the performance overhead as well as preserving the robustness of logic locking technique. We design the polymorphic logic gate using silicon nanowire field effect transistors (SiNW FETs) to replace the conventional Exclusive-OR (XOR)-based logic cone. We then evaluate the proposed technique based on security metric and performance overhead.

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

In this review article for Internet of Things (IoT) applications, important low-power design techniques for digital and mixed-signal analog–digital converter (ADC) circuits are presented. Emerging low voltage logic devices and non-volatile memories (NVMs) beyond CMOS are illustrated. In addition, energy-constrained hardware security issues are reviewed. Specifically, light-weight encryption-based correlational power analysis, successive approximation register (SAR) ADC security using tunnel field effect transistors (FETs), logic obfuscation using silicon nanowire FETs, and all-spin logic devices are highlighted. Furthermore, a novel ultra-low power design using bio-inspired neuromorphic computing and spiking neural network security are discussed.

Syringe-Injectable Electronics with a Plug-and-Play Input/Output Interface.

Syringe-injectable mesh electronics represent a new paradigm for brain science and neural prosthetics by virtue of the stable seamless integration of the electronics with neural tissues, a consequence of the macroporous mesh electronics structure with all size features similar to or less than individual neurons and tissue-like flexibility. These same properties, however, make input/output (I/O) connection to measurement electronics challenging, and work to-date has required methods that could be difficult to implement by the life sciences community. Here we present a new syringe-injectable mesh electronics design with plug-and-play I/O interfacing that is rapid, scalable, and user-friendly to nonexperts. The basic design tapers the ultraflexible mesh electronics to a narrow stem that routes all of the device/electrode interconnects to I/O pads that are inserted into a standard zero insertion force (ZIF) connector. Studies show that the entire plug-and-play mesh electronics can be delivered through capillary needles with precise targeting using microliter-scale injection volumes similar to the standard mesh electronics design. Electrical characterization of mesh electronics containing platinum (Pt) electrodes and silicon (Si) nanowire field-effect transistors (NW-FETs) demonstrates the ability to interface arbitrary devices with a contact resistance of only 3 Ω. Finally, in vivo injection into mice required only minutes for I/O connection and yielded expected local field potential (LFP) recordings from a compact head-stage compatible with chronic studies. Our results substantially lower barriers for use by new investigators and open the door for increasingly sophisticated and multifunctional mesh electronics designs for both basic and translational studies.

Theoretical Study of Ballistic Transport in Silicon Nanowire and Graphene Nanoribbon Field-Effect Transistors Using Empirical Pseudopotentials

We present a theoretical study of the ballistic performance of gate-all-around field-effect transistors (FETs) with channels consisting of armchair-edge graphene nanoribbons (aGNRs) of various widths and silicon nanowires (SiNWs) with square cross sections. We apply an atomistic quantum transport formalism based on empirical pseudopotentials. Our results show that the turn-OFF behavior of aGNRFETs is seriously affected by source-to-drain tunneling at short channel lengths (e.g., below 10 nm for 3-aGNRs). Defining the threshold voltage ${\textit V}_{\textsf {th}}$ as the gate bias at which the current reaches a given $I_{ \mathrm{\scriptscriptstyle OFF}} = 0.4~\mu \text{A}/\mu \text{m}$ , devices with a 5-nm channel length can reach a maximum current of only $400~\mu \text{A}/\mu \text{m}$ at a gate overdrive ${\textit V}_{\textit {GS}}-{\textit V}_{\textsf {th}} = 0.25$ V (corresponding to an assumed ${V}_{\textsf DD}$ of about 0.4 V). In contrast, SiNWFETs remain immune from source-to-drain tunneling even at 5 nm and show an almost ideal subthreshold swing, a satisfactory current of $1000~\mu \text{A}/\mu \text{m}$ at the same gate overdrive of 0.25 V, and a reasonable ${\textit I}_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ ratio around $2\times 10^{3}$ .

Investigation of the effect of finite-sized ions on the nanowire field-effect transistor in electrolyte concentration using a modified Poisson–Boltzmann model

ABSTRACTOne-dimensional (1D) nanowire field-effect transistors (FETs) have recently played a major role in sensing applications. Due to charging of the surface functional chemical groups with protonation and deprotonation, the transport properties of these nanowire transistors affect the aqueous environment, altering the electrical double layer (EDL) potential drops and charge distributions in the electrolyte concentration. In this work, we have implemented the simple modified Poisson–Boltzmann (MPB) theory in a 1D silicon nanowire FET, and the effect of the various finite sizes of ions in z:z symmetric electrolyte concentration was investigated. For a given ionic concentration and surface charge, the EDL potential drop, accumulation of charges and the charge distributions of NaCl and CsCl ions were studied. From the MPB model results with the nanowire FET, it was observed that the potential drop of the EDL depends on the size of the ions in the electrolyte. The study of various electrostatic investigations of finite-sized ions was successfully done by implementing the MPB model on a silicon nanowire FET. It can be used in both chemical and biological sensors.

Effect of Nanowire-dielectric Interface on the Hysteresis of Solution Processed Silicon Nanowire FETs

Silicon nanowires (Si NW) are ideal candidates for low-cost solution processed field effect transistors (FETs) due to the ability of nanowires to be dispersed in solvents, and demonstrated high charge carrier mobility. The interface between the nanowire and the dielectric plays a crucial role in the FET characteristics, and can be responsible for unwanted effects such as current hysteresis during device operation. Thus, optimal nanowire- dielectric interface is required for low-hysteresis FET performance. Here we show that NW FET hysteresis mostly depends on the nature of the dielectric material by directly comparing device characteristics of dual gate Si NW FETs with bottom SiO2 gate dielectric and top hydrophobic fluoropolymer gate dielectric. As the transistor semiconducting nanowire channel is identical in both tops and bottom operational regimes, the performance differences originate from the nature of the nanowire-dielectric interface. Thus, very high 30 volt hysteresis is observed for forward and reverse gate bias scans with SiO2 interface; however, hysteresis is significantly reduced to 6 volt for the fluoropolymer dielectric interface. The differences in hysteresis are ascribed to the polar OH- groups present at SiO2/Si nanowire interface, and mostly absent at fluoropolymer/Si nanowire interface. We further demonstrate that high density of charge traps for bottom gate SiO2 interface (1× 1013cm-2) is reduced by over an order of magnitude for top-fluoropolymer gate interface (7.5 × 1011 cm-2), therefore highlighting the advantage of hydrophobic polymer gate dielectrics for nanowire field-effect transistor applications.

Effect of eccentricity on junction and junctionless based silicon nanowire and silicon nanotube FETs

In this paper, the effect of eccentricity on Junction-based Silicon Nanowire FET, Junction-based Silicon Nanotube FET, Junctionless-based Silicon Nanowire FET, and Junctionless-based Silicon Nanotube FET is investigated. Three kinds of eccentric structures are considered here. The impact of eccentricity on effective gate oxide thickness thereby gate oxide capacitance, and effective channel width are studied using 3D numerical simulations. Average radius of an ellipse is used to generate a model which captures the impact of eccentricity on gate oxide capacitance, and verified using TCAD simulations in MOS nanowire structure. The impact of eccentricity on ON current (ION), OFF current (IOFF), ION/IOFF ratio, and Unity gain cutoff frequency are investigated. Eccentricity increases the effective gate oxide thickness, the effective channel width, ION, and IOFF but reduces ION/IOFF ratio.

Feasibility Study of Extended-Gate-Type Silicon Nanowire Field-Effect Transistors for Neural Recording.

In this research, a high performance silicon nanowire field-effect transistor (transconductance as high as 34 µS and sensitivity as 84 nS/mV) is extensively studied and directly compared with planar passive microelectrode arrays for neural recording application. Electrical and electrochemical characteristics are carefully characterized in a very well-controlled manner. We especially focused on the signal amplification capability and intrinsic noise of the transistors. A neural recording system using both silicon nanowire field-effect transistor-based active-type microelectrode array and platinum black microelectrode-based passive-type microelectrode array are implemented and compared. An artificial neural spike signal is supplied as input to both arrays through a buffer solution and recorded simultaneously. Recorded signal intensity by the silicon nanowire transistor was precisely determined by an electrical characteristic of the transistor, transconductance. Signal-to-noise ratio was found to be strongly dependent upon the intrinsic 1/f noise of the silicon nanowire transistor. We found how signal strength is determined and how intrinsic noise of the transistor determines signal-to-noise ratio of the recorded neural signals. This study provides in-depth understanding of the overall neural recording mechanism using silicon nanowire transistors and solid design guideline for further improvement and development.

Top-down fabrication of silicon-nanowire arrays for large-scale integration on a flexible substrate for achieving high-resolution neural microelectrodes

In order to implement a nanowire-integrated device, well-aligned arrays of a silicon nanowires are necessary for scalable and repeatable mass production. Especially for biomedical applications in neural engineering, device flexibility robust to mechanical bending, without compromising the electrical performance, is a key issue to be resolved. In this paper, a simple fabrication method and the large-scale integration of silicon-nanowire arrays is proposed by combining top---down fabrication with nanowire transfer on flexible substrate for applications in high-resolution neural stimulation microelectrodes. The arrayed silicon nanowires are fabricated on a p-type, (111)-oriented, single-crystalline-silicon substrate by a top-down process that includes silicon dry etching, silicon wet etching, and wet oxidation. After the fabrication of nanowire arrays, the device is transferred to flexible substrate using polyimide coating, electrode formation, and substrate removal. In order to verify the feasibility of the proposed method, a silicon-nanowire field-effect transistor (FET) switch is implemented and evaluated. The results of the proposed method show an excellent potential for high-resolution neural stimulation microelectrodes.

Detection of K+ Efflux from Stimulated Cortical Neurons by an Aptamer-Modified Silicon Nanowire Field-Effect Transistor.

The concentration gradient of K+ across the cell membrane of a neuron determines its resting potential and cell excitability. During neurotransmission, the efflux of K+ from the cell via various channels will not only decrease the intracellular K+ content but also elevate the extracellular K+ concentration. However, it is not clear to what extent this change could be. In this study, we developed a multiple-parallel-connected silicon nanowire field-effect transistor (SiNW-FET) modified with K+-specific DNA-aptamers (aptamer/SiNW-FET) for the real-time detection of the K+ efflux from cultured cortical neurons. The aptamer/SiNW-FET showed an association constant of (2.18 ± 0.44) × 106 M-1 against K+ and an either less or negligible response to other alkali metal ions. The α-amino-3-hydroxy-5-methyl-4-isoxazolepropionic acid (AMPA) stimulation induced an outward current and hyperpolarized the membrane potential in a whole-cell patched neuron under a Na+/K+-free buffer. When neurons were placed atop the aptamer/SiNW-FET in a Na+/K+-free buffer, AMPA (13 μM) stimulation elevated the extracellular K+ concentration to ∼800 nM, which is greatly reduced by 6,7-dinitroquinoxaline-2,3-dione, an AMPA receptor antagonist. The EC50 of AMPA in elevating the extracellular K+ concentration was 10.3 μM. By stimulating the neurons with AMPA under a normal physiological buffer, the K+ concentration in the isolated cytosolic fraction was decreased by 75%. These experiments demonstrate that the aptamer/SiNW-FET is sensitive for detecting cations and the K+ concentrations inside and outside the neurons could be greatly changed to modulate the neuron excitability.

Study of silicon nanowire field effect transistor with different oxide material using fettoy simulator

As the MOSFET gate length enters the nanometer regime, short channel effects (SCE) such as threshold voltage (VT) roll off and drain- induced- barrier- lowering becomes increasingly significant, which limits the scaling capability of planar bulk or silicon-on-insulator (SOI) MOSFET. At the same time the relatively low carrier mobility in silicon may also degrade the MOSFET device performance. For these reasons, various novel device structures and materials such as silicon nanowire transistors, carbon nanotubes, new channel materials, molecular transistors are being extensively explored. Among all these, promising post CMOS structures, the silicon nanowire transistor (SNWT) has its unique advantage - The SNWT is based on silicon a material that the semiconductor industry has been working on for over forty years; it would be really attractive to stay on silicon and also achieve good device matrices that nano-electronics provides. The main objective of this paper is to present Simulation of silicon Nanowire field Effect Transistor (SNWFET) with different oxide having different k value and observe the effect on characteristics thereon using Fettoy Simulator.

Nanowire sensors monitor bacterial growth kinetics and response to antibiotics.

Miniaturized and cost-efficient methods aiming at high throughput analysis of microbes are of great importance for the surveillance and control of infectious diseases and the related issue of antimicrobial resistance. Here we demonstrate a miniature nanosensor based on a honeycomb-patterned silicon nanowire field effect transistor (FET) capable of detection of bacterial growth and antibiotic response in microbiologically relevant nutrient media. We determine the growth kinetics and metabolic state of Escherichia coli cells in undiluted media via the quantification of changes in the source-drain current caused by varying pH values. Furthermore, by measuring the time dependent profile of pH change for bacterial cultures treated with antibiotics, we demonstrate for the first time the possibility of electrically distinguishing between bacteriostatic and bactericidal drug effects. We believe that the use of such nanoscopic FET devices enables addressing parameters that are not easily accessible by conventional optical methods in a label-free format, i.e. monitoring of microbial metabolic activity or stress response.

Flexible field-effect transistors using top-down fabrication of (111)-silicon nanowires and wafer-level transfer process for neural prostheses

In this paper, a simple fabrication method and a large-scale integration of silicon nanowires by combining top-down fabrication with wafer-level transfer process on a flexible substrate is presented. For applications in high-resolution neural prostheses, silicon-nanowire field-effect transistor (FET) switches on a flexible substrate is developed and integrated to microelectrode array (MEA). The fabrication process is developed, and results of (111)-silicon nanowire array and nanowire devices on flexible substrate are shown. The overall device thickness is sufficiently thin for high device flexibility. The quantitative current model is used to analyze the operation mechanism of silicon-nanowire FET. The proposed method can implement the width and thickness of silicon nanowires independently, which can result in higher performance characteristics. The electrical characteristics of the fabricated silicon-nanowire FET switch are measured. The current on/off ratio is above 1×107 and average RON is calculated to be 41kΩ, which shows similar results with the simulation. These results of proposed method show a strong potential for applications in high-resolution neural prostheses.