Abstract
In this study, we demonstrate the static random access memory (SRAM) characteristics generated by weak impact ionization in bendable field-effect transistors (FETs) with n+-p-n+ silicon nanowire (SiNW) channels. Our bendable SiNW FETs show not only superior switching characteristics such as an on/off current ratio of ~105 and steep subthreshold swing (~5 mV/dec) but also reliable SRAM characteristics. The SRAM characteristics originate from the positive feedback loops in the SiNW FETs generated by weak impact ionization. This paper describes in detail the operating mechanism of our device and demonstrates the potential of bendable SiNW FETs for future SRAM applications.
Highlights
Electronic devices fabricated on lightweight, bendable, transparent, and low cost plastic substrates are believed to have great potential application in future wearable electronics
feedback FETs (FBFETs) with p+-i-n+ diodes have been successfully utilized for dynamic random access memory (DRAM) without any external capacitor owing to their sharp switching and hysteresis characteristics[21,22,23]
For the positive feedback loop generated by weak impact ionization, capacitorless DRAM functionalities have been reported in recent years[29,30]
Summary
Electronic devices fabricated on lightweight, bendable, transparent, and low cost plastic substrates are believed to have great potential application in future wearable electronics. Various promising devices that realize steep slopes beyond that of the MOSFET technology have been introduced, including tunneling FETs (TFETs)[6,7,8,9], impact ionization FETs10–12, and feedback FETs (FBFETs)[13,14] These devices that operate in innovative operating mechanisms such as band-to-band tunneling (BTBT), avalanche breakdown, and positive feedback loop show low SS values, they suffer from some major drawbacks in their device application. In spite of the superior DRAM functionalities, the data-retention time is limited because there is no neutral region of the body in fully depleted silicon-on-insulator (FD SOI); back-gate biasing is required to accommodate the majority carriers in the accumulated back channel. This makes the implementation of SRAMs difficult. We demonstrate the feasibility of full SRAM operations in our PD SiNW FET which is connected in series with an access transistor by computer simulation tool
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