Abstract
Silicon nanowires (Si NW) are ideal candidates for low-cost solution processed field effect transistors (FETs) due to the ability of nanowires to be dispersed in solvents, and demonstrated high charge carrier mobility. The interface between the nanowire and the dielectric plays a crucial role in the FET characteristics, and can be responsible for unwanted effects such as current hysteresis during device operation. Thus, optimal nanowire- dielectric interface is required for low-hysteresis FET performance. Here we show that NW FET hysteresis mostly depends on the nature of the dielectric material by directly comparing device characteristics of dual gate Si NW FETs with bottom SiO2 gate dielectric and top hydrophobic fluoropolymer gate dielectric. As the transistor semiconducting nanowire channel is identical in both tops and bottom operational regimes, the performance differences originate from the nature of the nanowire-dielectric interface. Thus, very high 30 volt hysteresis is observed for forward and reverse gate bias scans with SiO2 interface; however, hysteresis is significantly reduced to 6 volt for the fluoropolymer dielectric interface. The differences in hysteresis are ascribed to the polar OH- groups present at SiO2/Si nanowire interface, and mostly absent at fluoropolymer/Si nanowire interface. We further demonstrate that high density of charge traps for bottom gate SiO2 interface (1× 1013cm-2) is reduced by over an order of magnitude for top-fluoropolymer gate interface (7.5 × 1011 cm-2), therefore highlighting the advantage of hydrophobic polymer gate dielectrics for nanowire field-effect transistor applications.
Highlights
Solution-processed printable electronics using semiconducting inks have opened up the possibility of various low-cost electronic devices for large area applications such as electronic circuits [1], sensors [2] and light emitters [3]
We studied the effect of nanowire –dielectric interface on hysteresis in Silicon nanowires (Si NW) field-effect transistors with channel consisting of multiple nanowires by directly comparing SiO2 and polymer dielectrics interfaces in the same dual-gate field effect transistors (FETs)
By directly comparing dual gate nanowire FET operation using bottom SiO2 gate dielectric accompanied by high current hysteresis of about 30V, with operation using top hydrophobic polymer gate dielectric and much lower hysteresis of only 6 V, we clearly demonstrate the performance advantages of the polymer dielectric
Summary
Solution-processed printable electronics using semiconducting inks have opened up the possibility of various low-cost electronic devices for large area applications such as electronic circuits [1], sensors [2] and light emitters [3] Nanomaterials such as inorganic single crystalline nanowires offer both high charge carrier mobilities [4] and solution processability [1] [2] [5]. We show that Si NW FET performance in bottom gate mode with SiO2 dielectric cannot be noticeably improved by an encapsulation with polymer layers, further highlighting the importance of the correct nanowire-dielectric operational interface for high performance nanowire devices. These studied directly demonstrate the superior performance of fluoropolymer gate dielectric for nanowire -based FETs
Sign-in/Register to view highlights & summary 
Published Version (
Free)
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
