Silicon Metal Oxide Semiconductor Field Research Articles

Highly stable Si MOSFET-type humidity sensor with ink-jet printed graphene quantum dots sensing layer

This paper investigates humidity sensing characteristics of a silicon metal oxide semiconductor field effect transistor (Si MOSFET)-based humidity sensor having horizontal floating-gate (FG) interdigitated with control-gate (CG). The sensing material of the humidity sensor is graphene quantum dots (GQDs), deposited locally on the interdigitated CG-FG area by an ink-jet printing method using a small amount of the GQDs solution. The humidity sensing characteristics of the sensor are measured as a parameter of relative humidity (RH). The response of the humidity sensor is 78 % to the humid air of 81.3 % RH. We also adopt a pulsed pre-bias method to improve the response and recovery characteristics of the humidity sensor. The response and recovery characteristics of the sensor can be improved 30 % and 40 % respectively by applying a pre-bias of 2 V and -1 V to the CG. In all relative humidity ranges, the FET-type humidity sensor has highly stable and reproducible characteristics in long-term measurements for 5 months.

Optimized Design of 1 MHz Intermediate Bus Converter Using GaN HEMT for Aerospace Applications

This paper presents the possibility of using Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) instead of the conventional silicon metal oxide semiconductor field effect transistor (MOSFET) to implement a high-frequency intermediate bus converter (IBC) as part of a typical distributed power architecture used in a space power application. The results show that processing the power at greater frequencies is possible with a reduction in mass and without impacting the system efficiency. The proposed solution was experimentally validated by the implementation of a 1 MHz zero-voltage and zero-current switching (ZVZCS) current-fed half-bridge converter with synchronous rectification compared with the same converter using silicon as the standard technology on power switches and working at 100 kHz. In conclusion, the replacement of silicon (Si) transistors by GaN HEMTs is feasible, and GaN HEMTs are promising next-generation devices in the power electronics field and can coexist with silicon semiconductors, mainly in some radiation-intensive environments, such as power space converters. The best physical properties of GaN HEMTs, such as inherent radiation hardness, low on resistance and parasitic capacitances, allow them to switch at higher frequencies with high efficiency achieving higher power density. We present an optimized design procedure to guaranty the zero-voltage switching condition that enables the power density to be increased without a penalization of the efficiency.

Comparison of the Effects of Nonlinearities for Si MOSFET and GaN E-HEMT Based VSIs

Nonlinearities in voltage source inverters (VSIs) such as; dead time, switching time, delay time, voltage drops on the power switches, parasitic capacitance, etc., are considered to be the main sources of the output voltage distortions. These distortions result in low-order harmonics in the output current, which in turn increase core losses and create torque ripples. In particular, for low-speed applications with low-inductance motors, the control performance and the stability of the system degrades substantially, especially when the system operates in the low-torque region. In this work, the effects of these nonlinearities on the phase current and on the current control of the silicon (Si) metal oxide semiconductor field effect transistor (MOSFET) based VSI are investigated with an air cored low inductance permanent magnet synchronous motor. Furthermore, Gallium nitride (GaN) enhancement mode high electron mobility transistor (E-HEMT) based VSI is proposed to overcome this problem. Next, improvements in the current control process are demonstrated by comparing the experimental results obtained by using GaN E-HEMT and Si MOSFET based VSIs. Results show that GaN E-HEMT based VSI is a better choice for applications, which require a high bandwidth control.

Improved CO gas detection of Si MOSFET gas sensor with catalytic Pt decoration and pre-bias effect

This paper investigates carbon monoxide (CO) gas sensing performance in a silicon metal-oxide semiconductor field effect transistor (Si MOSFET)-based gas sensor having a structure in which a floating-gate (FG) and a control-gate (CG) are interdigitated in a horizontal direction. The sensing material, indium oxide (In2O3) nanoparticles, is formed by an inkjet printing process between the FG covered with an insulator stack and exposed CG. Decorating the sensing layer with catalytic Pt and applying pulsed pre-bias are introduced as a method to improve CO gas sensing characteristics of the MOSFET sensor. First, CO gas sensing performance with Pt concentration and operating temperature is studied. The sensing performance is measured at 200 °C mainly by applying pulses to the CG. The response, response and recovery times of the MOSFET sensor are significantly enhanced with catalytic Pt decoration. In this work, 5% Pt decoration shows the best sensing characteristics. Response and recovery times are improved by 65% and 70%, by applying a pre-bias of 2 V and −2 V to the CG during response and recovery, respectively.

Multimode silicon nanowire transistors.

The combined capabilities of both a nonplanar design and nonconventional carrier injection mechanisms are subject to recent scientific investigations to overcome the limitations of silicon metal oxide semiconductor field effect transistors. In this Letter, we present a multimode field effect transistors device using silicon nanowires that feature an axial n-type/intrinsic doping junction. A heterostructural device design is achieved by employing a self-aligned nickel-silicide source contact. The polymorph operation of the dual-gate device enabling the configuration of one p- and two n-type transistor modes is demonstrated. Not only the type but also the carrier injection mode can be altered by appropriate biasing of the two gate terminals or by inverting the drain bias. With a combined band-to-band and Schottky tunneling mechanism, in p-type mode a subthreshold swing as low as 143 mV/dec and an ON/OFF ratio of up to 104 is found. As the device operates in forward bias, a nonconventional tunneling transistor is realized, enabling an effective suppression of ambipolarity. Depending on the drain bias, two different n-type modes are distinguishable. The carrier injection is dominated by thermionic emission in forward bias with a maximum ON/OFF ratio of up to 107 whereas in reverse bias a Schottky tunneling mechanism dominates the carrier transport.

Computational study of heterojunction graphene nanoribbon tunneling transistors with p-d orbital tight-binding method

The graphene nanoribbon (GNR) tunneling field effect transistor (TFET) has been a promising candidate for a future low power logic device due to its sub-60 mV/dec subthreshold characteristic and its superior gate control on the channel electrons due to its one-dimensional nature. Even though many theoretical studies have been carried out, it is not clear that GNR TFETs would outperform conventional silicon metal oxide semiconductor field effect transistors (MOSFETs). With rigorous atomistic simulations using the p/d orbital tight-binding model, this study focuses on the optimization of GNR TFETs by tuning the doping density and the size of GNRs. It is found that the optimized GNR TFET can operate at a half of the supply voltage of silicon nanowire MOSFETs in the ballistic limit. However, a study on the effects of edge roughness on the performance of the optimized GNR TFET structure reveals that experimentally feasible edge roughness can deteriorates the on-current performance if the off-current is normalized with the low power requirement specified in the international technology roadmap for semiconductors.

Silicon carbide JFET reverse conduction characteristics and use in power converters

Recent advances have resulted in the availability of a new generation of silicon carbide (SiC) junction field effect transistors (JFETs), which unlike previous generations, exhibit highly desirable normally off characteristics. Normally off SiC JFETs are characterised with particular focus on previously unknown reverse conduction characteristics. Refinements are proposed to JFET gate driving circuits that allow their implementation as a single-chip solution. Reverse recovery characteristics of SiC JFETs were measured using diode testing techniques and found to be significantly faster than typical silicon metal oxide semi-conductor field effect transistor (MOSFET) body diodes. SiC JFETs are compared with silicon MOSFETs in power factor correction boost converters, including a real-world application where superior power conversion efficiency utilising SiC JFETs is demonstrated.

A new analytical subthreshold model of SRG MOSFET with analogue performance investigation

For the first time, a pseudo-two-dimensional (2D) approach is extended from a rectangular device structure to a cylindrical one. A pseudo-2D model applying Gauss's law in the cylindrical channel depletion region for undoped or lightly doped surrounding gate (SRG) silicon metal oxide semiconductor field effect transistor (MOSFETs) working in subthreshold regime is presented. From this pseudo-2D analysis, electrostatic potentials, current characteristics, the threshold voltage roll-off, the drain-induced barrier lowering and the subthreshold swing are explicitly modelled. The obtained analytical model has been extended to develop a model for transconductance-to-drain current ratio (g m/I d) in weak inversion regime. Analogue figures of merit of SRG MOSFETs are studied, including transconductance efficiency g m/I d, intrinsic gain and output resistance. The trends related to their variations along the downscaling of dimension are provided. In order to validate our model, the modelled expressions are compared with the simulated characteristics obtained from ATLAS device simulator.

Drain-induced barrier-lowering effects on threshold voltage in short-channel strained Si metal-oxide semiconductor field transistor

Based on strained silicon metal-oxide semiconductor field transistor (MOSFET) structure, the distribution of surface potential is obtained by solving two-dimensional Poisson equation, and the threshold voltage model is built. According to calculation results, the dependence of threshold voltage on germanium content of relaxed Si1－βGeβ, channel length, voltage of drain, doping content of substrate and channel are studied in detail, and the influence of drain-induced barrier-lowering on scaled strained silicon MOSFET is obtained, which can provide important reference for the design of strained silicon MOSFET device and circuit.

Trapped charge dynamics in a sol–gel basedTiO2 high-k gate dielectric silicon metal–oxide–semiconductor field effect transistor

We have studied the response of a sol–gel basedTiO2, highk dielectric field effect transistor structure to microwave radiation. Under fixed biasconditions the transistor shows frequency dependent current fluctuations when exposed tocontinuous wave microwave radiation. Some of these fluctuations take the form of highQ resonances. The time dependent characteristics of these responseswere studied by modulating the microwaves with a pulse signal. Themeasurements show that there is a shift in the centre frequency of these highQ resonances when the pulse time is varied. The measured lifetime of these resonances is highenough to be useful for non-classical information processing.

Effect of microwave irradiation on the emission and capture dynamics in silicon metal oxide semiconductor field effect transistors

Microwave irradiation causes voltage fluctuations in solid state nanodevices. Such an effect is relevant in atomic electronics and nanostructures for quantum information processing, where charge or spin states are controlled by microwave fields and electrically detected. Here, the variation of the characteristic times of the capture and emission of a single electron by an interface defect in submicron metal oxide semiconductor field effect transistor is calculated and measured as a function of the microwave power. In the model, the frequency of the voltage modulation is assumed to be large if compared to the inverse of the characteristic times. The variation of the characteristic times under microwave irradiation is quantitatively predicted from the microwave frequency dependent stationary current generated by the voltage fluctuation itself. The expected values agree with the experimental measurements. The reported effect has to be carefully considered in electrically detected single electron spin resonance experiments. In such experiments, a spurious change of the power of the microwave coupled to the device could be confused with the single spin resonance.

Carbon Nanotube Applications in Microelectronics

The extraordinary characteristics of carbon nanotubes make them a promising candidate for applications in microelectronics. Catalyst-mediated chemical vapor deposition growth is very well suited for selective in-situ growth of nanotubes compatible with the requirements of microelectronics technology. This deposition method can be exploited for carbon nanotube vias. Semiconducting single-walled tubes can be successfully operated as carbon nanotube field effect transistors (CNTFET). A simulation of an ideal CNTFET is presented and compared with the requirements of the ITRS roadmap. Finally, we compare an upgraded CNTFET with the most advanced silicon metal oxide semiconductor field effect transistors and discuss integration issues.

Evidence for ballistic transport of two-dimensional electron gas at liquid-nitrogen temperatures in a silicon metal–oxide semiconductor field effect transistor with a neck in the middle

The transconductance of a silicon metal–oxide semiconductor field effect transistor with a neck in the middle was measured at liquid-nitrogen temperatures. The narrowest part of the gate with p+ isolations is 0.24 μm wide and about 0.2 μm long. The transconductance shows a peaked structure near the threshold voltage. The calculated transconductance based on the ballistic transport model of two-dimensional electron gas explains well the peaked structure.

Quantitative study of metal–oxide semiconductor field effect transistor damage induced by scanning tunneling microscope lithography

The channel areas of n-channel silicon metal–oxide semiconductor field effect transistor (MOSFET) devices have been patterned with an air-operated scanning tunneling microscope (STM) and processed to completion. Gate oxide thickness modulations greater than 80 Å have been achieved with this technique. The impact of the STM process step on the silicon/insulator interface has been characterized with two-level charge pumping. The number of interface traps attributable to the STM lithography process is roughly 7×1010/cm2 eV. Additionally, transistor parameters from the STM FETs are compared with those from virgin FETs to assess any possible leakage current and mobility degradation induced by the STM process.

Design and characterization of compact 100 nm-scale silicon metal–oxide–semiconductor field effect transistors

Ultracompact n-channel silicon metal–oxide–semiconductor field effect transistors (MOSFETs) have been fabricated using electron beam nanolithography for all critical levels leading to a first demonstration of silicon MOSFETs which meet 100 nm ground rules. The smallest devices fabricated have active areas which measure only 700 nm×150 nm and are enclosed by a narrow trench isolation scheme. Devices of this size and with physical gate lengths of 120 nm and widths of 150 nm display an extrinsic transconductance of 410 mS/mm at room temperature. This level of miniaturization and performance arises in part from direct application of conventional scaling principles and in part from implementation of a novel device configuration. This article discusses the design of these devices as well as details of their electrical characteristics.

Fabrication of compact 100 nm-scale silicon metal–oxide–semiconductor field effect transistors

The fabrication of exploratory silicon metal–oxide–semiconductor field effect transistors in which all device levels meet 100 nm groundrules is reported. The device design incorporates several novel features which allow for an ultracompact structure. These features include shallow trench isolation, over-the-gate contacts, fully overlapped source, drain and gate contacts and shallow source and drain extensions. This article offers a detailed description of the fabrication process, with an emphasis on high resolution, high accuracy electron beam nanolithography and new reactive ion etching processes. Complete process integration is described which culminates in the successful fabrication of functional compact devices.