Fabrication of compact 100 nm-scale silicon metal–oxide–semiconductor field effect transistors

Abstract

The fabrication of exploratory silicon metal–oxide–semiconductor field effect transistors in which all device levels meet 100 nm groundrules is reported. The device design incorporates several novel features which allow for an ultracompact structure. These features include shallow trench isolation, over-the-gate contacts, fully overlapped source, drain and gate contacts and shallow source and drain extensions. This article offers a detailed description of the fabrication process, with an emphasis on high resolution, high accuracy electron beam nanolithography and new reactive ion etching processes. Complete process integration is described which culminates in the successful fabrication of functional compact devices.