Premolded copper leadframe substrate: an enabling technology for advanced unmolded substrate packages

Abstract

The trend of package miniaturization in the field of electronics is a key driver towards development of novel packages with superior electrical & thermal performances. Several power package designs use the solder bumping technology to improve RDSon & thermal resistance. These include the MOSFET BGA [Granada et al., 2003] and Flip Chip in a Leaded Molded Package [Joshi et al., 2004] (FLMP). Both packages attained low electrical and thermal resistances by providing short and unrestricted routes of the drain, source & gate contacts towards the package external, hence, towards the printed circuit board (PCB). The MOSFET BGA for example have direct source and gate contacts to the PCB through die solder bumps, while drain contacts are maximized through the use of leadframe substrate with peripheral protrusions or solder balls coplanar to the source bumps which are directly soldered to the board. The FLMP on the other hand is designed to have the die backside (drain contact of the MOSFET) soldered directly to the board while the source & gate contacts (leads of the package) are formed coplanar to the die backside. Both MOSFET BGA & FLMP are electrically & thermally versatile relative to its size. A new packaging idea has emerged by combining the best features of these two packages. This new package is called MaxFET. It is an unmolded substrate package, which adopts the FLMP direct soldering concept of die backside to the PCB, hence maximizing the drain connection. Source path of the package to the PCB is shortened by using leadframe substrate and ball attach technology such as that of the MOSFET BGA. The substrate is the main external framework of MaxFET package, thus electrical, thermal, mechanical and size considerations are significant factors in the design. Development of ultra-thin premolded leadframe substrate for MaxFET packaging will be detailed and discussed along with finite element analysis and preliminary reliability testing.