Silicon MESFET Research Articles

Correction to: Analytical modeling and simulation of a fully depleted three-gate silicon MESFET on SOI material

The original version of this article unfortunately contained errors. The language edits made in the original version has not been incorporated in the published version.

A Proposed Silicon Optical Electronic Integrated Circuit with Monolithic Integration of LED, OPFET and Receiver Circuit

The paper presents an improved model of Silicon Optical Electronic Integrated Circuit (SOIC). The objective is to improve our OEIC model i.e. OEIC Circuit with Two Metal Layer Silicon Waveguide and Low Power Photonic Receiver Circuit by increasing responsitivity by increasing the quantum efficiency without changing the basic approach. This can be done by using optically controlled silicon MESFET also called OPFET. We also introduced the transparent indium tin oxide gate which when combines with MESFET, acts as a pre-amplifier in OEIC. The optically controlled silicon MESFET is integrated here having improved responsitivity, low gate to source capacitance, less signal delay, reduced noise and increased quantum efficiency.

Optically Controlled Silicon MESFET Fabrication and Characterizations for Optical Modulator/Demodulator

An optically controlled silicon MESFET (OPFET) was fabricated by diffusion process to enhance the quantum efficiency, which is the most important optoelectronic device performance usually affected by ion implantation process due to large number of process induced defects. The desired impurity distribution profile and the junction depth were obtained solely with diffusion, and etching processes monitored by atomic force microscope, spreading resistance profiling and C-V measurements. With this approach fabrication induced defects are reduced, leading to significantly improved performance. The fabricated OPFET devices showed proper I-V characteristics with desired pinch-off voltage and threshold voltage for normally-on devices. The peak photoresponsivity was obtained at 620 ㎚ wavelength and the extracted external quantum efficiency from the photoresponse plot was found to be approximately 87.9%. This result is evidence of enhancement of device quantum efficiency fabricated by the diffusion process. It also supports the fact that the diffusion process is an extremely suitable process for fabrication of high performance optoelectronic devices. The maximum gain of OPFET at optical modulated signal was obtained at the frequency of 1 MHz with rise time and fall time approximately of 480 nS. The extracted transconductance shows the possible potential of device speed performance improvements for shorter gate length. The results support the use of a diffusion process for fabrication of high performance optoelectronic devices.

Representation of the solution to a model problem in semiconductor physics

We study a mixed type problem for the Poisson equation arising in the modeling of charge transport in semiconductor devices [V. Romano, 2D simulation of a silicon MESFET with a non-parabolic hydrodynamical model based on the maximum entropy principle, J. Comput. Phys. 176 (2002) 70–92; A.M. Blokhin, R.S. Bushmanov, A.S. Rudometova, V. Romano, Linear asymptotic stability of the equilibrium state for the 2D MEP hydrodynamical model of charge transport in semiconductors, Nonlinear Anal. 65 (2006) 1018–1038]. Unlike well-studied elliptic boundary-value problems in domains with smooth boundaries (see, for example, [O.A. Ladyzhenskaya, N.N. Uralceva, Linear and Quasilinear Elliptic Equations, Nauka, Moscow, 1973; D. Gilbarg, N.S. Trudinger, Elliptic Partial Differential Equations of Second Order, Springer-Verlag, Berlin, 1983]), our problem has two significant features: firstly, the boundary is not a smooth curve and, secondly, the type of boundary conditions is mixed (the Dirichlet condition is satisfied on the one part of the boundary whereas the Neumann condition on the other part). The well-posedness of the problem in Hölder and Sobolev spaces is proved. The representation of the solution to the problem is obtained in an explicit form.

Efficient time integration of the Boltzmann-Poisson system applied to semiconductor device simulation

This paper presents new efficient methods for performing the time integration of finite-difference WENO approximations of the Boltzmann-Poisson system applied to semiconductor device simulation. The developed methods are based on local time-step schemes for hyperbolic conservation laws which permit the use of different time increments at different positions in space. A strategy to dynamically adapt the space-time grid according to the actual stability criteria imposed by the CFL-condition is proposed. The resulting numerical schemes are used to simulate the electron transport in a n+−n−n+ silicon diode and in a silicon MESFET. Several numerical tests and comparisons with computations performed with TVD Runge-Kutta type algorithms prove the efficiency of the presented time integration methods.

2D Simulation of a Silicon MESFET with a Nonparabolic Hydrodynamical Model Based on the Maximum Entropy Principle

A hydrodynamical model for electron transport in silicon semiconductors, which is free of any fitting parameters, has been formulated on the basis of the maximum entropy principle. The model considers the energy band to be described by the Kane dispersion relation and includes electron–nonpolar optical phonon and electron–acoustic phonon scattering. The set of balance equations of the model forms a quasilinear hyperbolic system and for its numerical integration a recent high-order shock-capturing central differencing scheme has been employed. Simulations of an n+–n–n+ silicon diode have been presented and comparison with Monte Carlo data shows the good accuracy of the model and performance of the numerical scheme. Here the results of simulations of a silicon MESFET in the two-dimensional case are presented. Both the model and the numerical scheme demonstrate their accuracy and efficiency as CAD tools for modeling realistic submicron electron devices.

MESFET's—Modelling and Fabrication Technology

Basic operating principles of silicon and GaAs MESFET's are described. Differences arising out due to their different velocity field dependence are outlined. Transient effects in short gate length devices are discussed. Analytical solution for the I-V characteristics based on gradual channel approximation and the effect of saturated drift velocity are discussed. Small signal equivalent circuit of a short gate length FET and the design parameters of a low noise device are described. Fabrication technology for a practical small signal FET is presented.

Simulation of MESFET device by streamline‐diffusion finite element methods

Uses a streamline‐diffusion finite element method, specially designed for semiconductor device models, to simulate silicon MESFET devices in two space dimensions. Considers the full hydrodynamic model, a simplified hydrodynamic model and drift‐diffusion model. The method, which reduces to the well‐known Scharfetter‐Gummel discretization for the conventional drift‐diffusion model in one space dimension, proves to be a robust numerical tool. It performs well also when the solution has layers of rapid variation across junctions which are not aligned with mesh lines. Makes comparisons for the different models. Finds a qualitative discrepancy between the solutions of the hydrodynamic model and the drift diffusion model. Observes a small difference, however, between the full and simplified hydrodynamic models.

Simulation of the hydrodynamic device model on distributed memory parallel computers

Stable and robust finite element methods for the convective hydrodynamic model of semiconductor devices are developed and implemented on distributed memory parallel computers. Specifically, a stable and accurate space-time and Galerkin/least-squares finite element formulation is developed for the hydrodynamic transport equations for the conservation laws. In addition, Galerkin finite element methods are employed for the Poisson and lattice thermal diffusion equations. The inclusion of the lattice thermal diffusion equation in the numerical solution of the convective hydrodynamic model is presented for the first time. Numerical results for a bipolar transistor are included to illustrate the effectiveness of the numerical methods. Numerical simulations of semiconductor devices using the convective hydrodynamic model require a significant amount of computations. A single-program-multiple-data (SPMD) programming model is proposed for the implementation of the hydrodynamic model on distributed memory parallel computers. Employing the SPMD programming model, a serial program developed on a workstation can be converted into a parallel program with minimal changes. The parallel program has been ported to a wide range of distributed memory parallel computers including the iPSC/860 hypercube, the Touchstone Delta machine, and the IBM SP-1. Parallel performance results are reported for a bipolar transistor, silicon MESFET and diodes. The results indicate that the parallel hydrodynamic device simulator exhibits excellent speedups and scalability on distributed memory parallel computers with minimum communication overhead.

A p-channel coupled delta-doped silicon MESFET grown by molecular beam epitaxy

Experimental realization of a new p-channel Si MESFET structure, utilizing two boron /spl delta/-doped layers placed in close proximity with one another as the conducting channel, is reported for the first time. This simple homoepitaxially grown Si structure exhibits not only higher sheet carrier density but also higher hole mobility than those of a single /spl delta/-doped layer. The measured transconductance of the device is 1.44 mS/mm at 300 K with a gate length of 5 /spl mu/m, which is a factor of 1.7 higher than the single /spl delta/-doped layer Si MESFET for the same dose in each /spl delta/-doped layer. >

A fully analytical back-gate bias model for n-channel silicon MESFETs with back channel implant

In this paper, a fully analytical back-gate bias effect model for n-channel silicon MESFET devices is presented. As verified by the PISCES results, the analytical n-channel silicon MESFET back-gate bias effect model provides a good accuracy in the internal potential distribution and the threshold voltage as the back gate bias is changed.

A device model for an ion-implanted MESFET with Half-Pearson and Half-Gaussian distribution under post-anneal conditions

A model is developed for an ion-implanted long channel silicon MESFET in terms of Half-Pearson-IV and Half-Gaussian distribution. Reasonable approximations have been made to obtain simplified solution of Poisson's equation. It is seen that approximate Gaussian profile and exact Half-Pearson-IV Half-Gaussian profile gives exactly the same I/sub d/-V/sub d/ curves. It is also observed that the threshold voltage gets reduced in the later case. >

SPRAM technology cultivates characteristics useful in many fields : Yukio Sato. JEE ( Japan) 26 (August 1992)

An accurate modeling of an ion-implanted silicon MESFET device has been carried out considering a Gaussian-exponential distribution of impurities. Although two-dimensional analysis is essential for the characterization of the short-channel and submicrometer FET devices, one-dimensional analysis is fairly accurate for a moderately long-channel MESFETs fabricated with a shallow implanted channel where the concentration is highly nonlinear with depth. Potential distribution, channel charge, threshold voltage, I–V characteristics, mobility and transconductance of the Si MESFET device have been evaluated. The results show closer agreement with the experimentally obtained values compared to those obtained considering only Gaussian distribution of impurity profile.

Microwave performance of GaAs-on-Si MESFETs with Si buffer layers

The incorporation of silicon-buffer layers is shown to be critical in attaining optimized microwave performance for GaAs on silicon MESFETs. A current gain cutoff frequency (f/sub t/) of 18 GHz and maximum power cutoff frequency (f/sub max/) of 30 GHz is reported for relaxed geometry devices. The low parasitic capacitance and excellent device isolation make this structure suitable for monolithic integration. >

Device physics and technology of complementary silicon MESFET's for VLSI applications

The development of a complete complementary MESFET technology is presented. The state-of-the-art, fully implanted, CMOS-like process uses Shannon implants together with a refractory silicide Schottky-gate material to combine high gate barrier heights with ease of fabrication. To minimize parasitic resistances, a unique sidewall structure and sidewall spacers are utilized to allow for self-aligned implantation of the source/drain regions. A self-aligned titanium silicidation technique is employed to minimize sheet and contact resistance of the source/drain regions. The SUPREM process simulator was employed extensively. The performance and modeling of device parameters (e.g., threshold voltage, gate leakage, and short-channel effects) and circuit parameters (e.g. standby current, noise margin, and speed) were accomplished through analytic formulations, the PISCES two-dimensional device simulator, and the SPICE circuit simulator. >

Subthreshold behaviour of silicon MESFETs on SOS and bulk silicon substrates : U. Magnusson, J. Tiren, H. Norde and H. Bleichner. Solid-St. Electron.32(11), 931 (1989)

Subthreshold behaviour of silicon MESFETs on SOS and bulk silicon substrates : U. Magnusson, J. Tiren, H. Norde and H. Bleichner. Solid-St. Electron.32(11), 931 (1989)

An improved silicon p-channel MESFET with a BF 2 implanted thin channel and ErSi 2 gate

To develop a process for making complementary silicon MESFETs it is of utmost importance to achieve high performance MESFETs. Especially the p-channel MESFETs need improvement of driving capability and switching speed. In this article, we will report results from a p-channel MESFET having an ErSi 2 gate, fabricated using bulk silicon technology. This device exhibits improved values of transconductances as compared to earlier fabricated devices. This is mainly due to the fabrication of a controlled thin channel, manufactured by the BF 2 implantation technique. Also, the subthreshold characteristics of this improved device is presented and is found to be comparable to MOS p-channel devices.

Subthreshold behaviour of silicon MESFETs on SOS and bulk silicon substrates

The subthreshold characteristics of silicon MESFETs manufactured using both bulk silicon and silicon-on-sapphire (SOS) technology, have been studied. n- and p-type devices have been investigated and their characteristics are presented here. The results show that the subthreshold behaviour for bulk devices in fully comparable with that of MESFETs, while the SOS devices show a somewhat lower value of subthreshold swing. A comparison between calculated and experimental behaviour is presented which yields information about the influence of the geometry and processing parameters of the subthreshold behaviour. It is proposed that the saturation subthreshold current for bulk transistors can be decreased by a proper design. An improvement for SOS devices, however, requires improved substrate material.

A fast approach for calculations of silicon MESFET characteristics from suprem doping profiles

A simple and fast program for process development of silicon n- and p-channel MESFETs has been developed. The program is used for rapid extraction of electrical and geometrical device parameters. Doping concentration profiles as predicted by SUPREM are used as input data. The simulations are controlled by a very simple input file. Channel thickness, IV-characteristics, pinch-off voltage, threshold voltage etc. may quickly be deduced. The program accounts for velocity saturation and includes doping concentration dependent mobilities. Also the effects of series resistances and contact resistances are included in the calculations. A comparison with fabricated devices is made and the agreement is found to be good. Comparisons of CPU time and accuracy is made to a general 2-D simulation program. This 2-D software was found to give somewhat better agreement to measured device characteristics but at the expense of at least 100 times longer execution times.

The effects of annealing on the switching characteristics of an ion-implanted silicon MESFET

The gate-source and gate-drain capacitances and the drain-source resistance are calculated in the region below pinchoff in the postimplanted annealed condition. It is observed that the capacitances decrease and the resistance increases compared to the case where diffusion of impurity ions due to annealing is not considered. P, B, As, Sb, Ga, and Al dopants are used for the calculation. The delay time is found to be mostly unaffected by annealing. The capacitances in the region above pinchoff show an increase as a result of annealing in the enhancement device compared to the case when diffusion is not taken into account. These capacitances are mainly due to the sidewalls of the space-charge region and are dependent on the threshold voltage, which decreases at higher anneal temperatures in the enhancement mode. >