Silicon Gate Research Articles

Distributed Amplifiers Based on Spindt-Type Field-Emission Nanotriodes

In this paper, we discuss and analyze the design of a high-frequency, broadband distributed amplifier (DA) based on a 2-D array of field-emission nanotriodes (FENT) consisting of self-aligned gate around a nanomaterial field emitter. We propose here a physics-based device model to characterize dc properties of individual FENTs and a transmission-line circuit for evaluating and optimizing relevant ac properties, including power gain and impedance matching. Our discussion starts from the FENT array's dc characteristics and covers its radio frequency and microwave properties, considering effects of array density, geometry, FENT dimensions, and nanoemitter work function, in order to maximize power gain and bandwidth for high-frequency applications (30-100 GHz). Finally, we consider the practical design of a transmitter front end for wireless systems, combining the FENT-array DA with a tapered open-ended waveguide antenna, significantly improving matching and power radiation efficiency. Our results are of interest for imaging, sensing, satellite communications, defense, and security at 94 GHz.

Fabrication of Self-Aligned Graphene FETs with Low Fringing Capacitance and Series Resistance

Graphene FETs with top-gate and buried-gate structure has been studied. The buried-gate structure shows less fringing capacitance and more reliable contacts. High-performance graphene transistors with self-aligned buried gates have been fabricated. The graphene transistor shows field-effect mobility of over 6,000 cm2/V · s according to the transconductance measurement. The contact resistance and intrinsic mobility have been extracted from both curve fitting and transfer length measurement, and the two results agree well. This result paves the way of high-quality graphene transistor technology for the RF application.

High Mobility P-Channel Thin-Film Transistors with Ultralarge-Grain Polycrystalline Silicon Formed Using Nickel-Induced Crystallization

In this study, p-channel polycrystalline silicon (poly-Si) thin-film transistors (TFTs) using an active layer of ultralarge-grain (ULG) silicon and multistack gate insulators of SiNx/SiO2 were fabricated and investigated. The ULG silicon thin films were formed by nickel (Ni)-induced crystallization and the average grain area of ULG silicon is 118 µm2. The field-effect mobility of p-channel ULG poly-Si TFTs was 111 cm2/(V·s), which can be sufficiently applied to high driving parts of display systems. The p-channel ULG poly-Si TFT has a low threshold voltage of -1.06 V, a high ON/OFF current ratio of 9.2×107, and a subthreshold swing of 0.27 V/decade. Moreover, the fabricated TFTs have stable characteristics under temperature and gate bias stress owing to the large grains and smooth surface. These results show that the ULG poly-Si TFTs are remarkably suitable for the application to a low power and high speed pixel-driving device in flat panel displays.

High Mobility P-Channel Thin-Film Transistors with Ultralarge-Grain Polycrystalline Silicon Formed Using Nickel-Induced Crystallization

In this study, p-channel polycrystalline silicon (poly-Si) thin-film transistors (TFTs) using an active layer of ultralarge-grain (ULG) silicon and multistack gate insulators of SiNx/SiO2 were fabricated and investigated. The ULG silicon thin films were formed by nickel (Ni)-induced crystallization and the average grain area of ULG silicon is 118 µm2. The field-effect mobility of p-channel ULG poly-Si TFTs was 111 cm2/(V·s), which can be sufficiently applied to high driving parts of display systems. The p-channel ULG poly-Si TFT has a low threshold voltage of -1.06 V, a high ON/OFF current ratio of 9.2×107, and a subthreshold swing of 0.27 V/decade. Moreover, the fabricated TFTs have stable characteristics under temperature and gate bias stress owing to the large grains and smooth surface. These results show that the ULG poly-Si TFTs are remarkably suitable for the application to a low power and high speed pixel-driving device in flat panel displays.

A fuzzy-logic-based approach to accurate modeling of a double gate MOSFET for nanoelectronic circuit design

The double gate (DG) silicon MOSFET with an extremely short-channel length has the appropriate features to constitute the devices for nanoscale circuit design. To develop a physical model for extremely scaled DG MOSFETs, the drain current in the channel must be accurately determined under the application of drain and gate voltages. However, modeling the transport mechanism for the nanoscale structures requires the use of overkill methods and models in terms of their complexity and computation time (self-consistent, quantum computations, …). Therefore, new methods and techniques are required to overcome these constraints. In this paper, a new approach based on the fuzzy logic computation is proposed to investigate nanoscale DG MOSFETs. The proposed approach has been implemented in a device simulator to show the impact of the proposed approach on the nanoelectronic circuit design. The approach is general and thus is suitable for any type of nanoscale structure investigation problems in the nanotechnology industry.

Digital Foundations: The Making of Silicon-Gate Manufacturing Technology

From 1960 onward, the expanding use of microchips played a major role in the establishment of the digital world. This paper examines the dominant manufacturing technology for microchips in this period: silicon-gate MOS technology . It reconstructs the development of silicon gate technology from its emergence at Bell Labs, Fairchild, General Micro-electronics, and Hughes in the mid-1960s to its stabilization at Intel and its augmentation with ion implantation at Mostek in the early 1970s. This article argues that silicon gate emerged at the convergence point of three contextual logics: material logic (the opportunities and constraints offered by materials and material capabilities), market logic (the dynamics of semiconductor markets), and competitive logic (the imperative of surviving in a fiercely competitive industry). Thus, this article is intended as a contribution to materials-centered studies and to recent interest on the connection between intentionality and materiality in technology and science.

Effect of Wet Surface Treatments on Amorphous Silicon Anneal and Gate Breakdown

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Performance characteristics of nanocrystalline diamond vacuum field emission transistor array

Nitrogen-incorporated nanocrystalline diamond (ND) vacuum field emission transistor (VFET) with self-aligned gate is fabricated by mold transfer microfabrication technique in conjunction with chemical vapor deposition (CVD) of nanocrystalline diamond on emitter cavity patterned on silicon-on-insulator (SOI) substrate. The fabricated ND-VFET demonstrates gate-controlled emission current with good signal amplification characteristics. The dc characteristics of the ND-VFET show well-defined cutoff, linear, and saturation regions with low gate turn-on voltage, high anode current, negligible gate intercepted current, and large dc voltage gain. The ac performance of the ND-VFET is measured, and the experimental data are analyzed using a modified small signal circuit model. The experimental results obtained for the ac voltage gain are found to agree with the theoretical model. A higher ac voltage gain is attainable by using a better test setup to eliminate the associated parasitic capacitances. The paper reveals the amplifier characteristics of the ND-VFET for potential applications in vacuum microelectronics.

P‐12: Self‐Aligned Bottom Gate LTPS Backplanes without Ion‐Implantation Process

AbstractWe developed and fabricated self‐aligned bottom gate LTPS backplanes without ion‐implantation process. CW green laser is used to fabricate polycrystalline silicon, and self‐alignment photo‐sensitive SiO coating film is used as a channel etch stopper. For high performance TFT backplanes, we developed CMOS process that allows us to operate CMOS circuits. Our developed TFT shows high mobility and high reliability.

Two-Dimensional Monte Carlo Simulation of DGSOI MOSFET Misalignment

In this paper, we investigate the gate misalignment effects in a 10-nm double-gate silicon-on-insulator MOSFET transistor with a 2-D Monte Carlo simulator. Quantum effects, which are of special relevance in such devices, are taken into account by using the multivalley effective conduction-band-edge method. Different gate misalignment configurations have been considered to study the impact on device performance, finding a current improvement when the gate misalignment increases the source-gate overlapping. Moreover, our results show that a 20% gate misalignment can be assumed for a drain current deviation smaller than 10%. Finally, the validity of the obtained results was assessed with a set of simulations for devices that have different gate lengths, silicon thicknesses, and oxide thicknesses.

The electron–hole bilayer tunnel FET

We propose a novel tunnel field-effect transistor (TFET) concept called the electron–hole bilayer TFET (EHBTFET). This device exploits the carrier tunneling through a bias-induced electron–hole bilayer in order to achieve improved switching and higher drive currents when compared to a lateral p–i–n junction TFET. The device principle and performances are studied by 2D numerical simulations. Output and transfer characteristics, as well as the impact of back gate bias, silicon thickness and gate length on the device behavior are evaluated. Device performances are compared for Si and Ge implementations. Nearly ideal average subthreshold slope (SSAVG∼10mV/dec over 7 decades of current) and ION/IOFF>108 at VD=VG=0.5V are obtained, due to the OFF–ON binary transition which leads to the abrupt onset of the band-to-band tunneling inside the semiconductor channel. Remarkably, for Ge EHBTFETs the ION (∼11μA/μm at VDD=0.5V) is 10× larger than in Ge tunnel FETs and 380× larger than in Si EHBTFETs.

Self-aligned patterning method of poly(aniline) for organic field-effect transistor gate electrode

We present a new manufacturing method for the bottom-gate type organic field-effect transistor (OFET) having a self-aligned gate electrode based on conducting poly(aniline). This method utilizes the possibility to turn the insulating emeraldine base (PANI-EB) form of poly(aniline) into the conducting emeraldine salt (PANI-ES) form by using UV exposure and photoacid generator (PAG) material. When the source–drain electrodes are used as the mask layer in the UV exposure step an optimal alignment between the gate electrode and source–drain electrodes can be reached, and the parasitic capacitance of the transistor can be minimized. We anticipate that the proposed concept also simplifies the fabrication of the transistors since no additional processing of the photoresist layers is needed to pattern the gate electrode or the gate insulator layer.

An Integrated Amorphous Silicon Gate Driver Circuit Using Voltage-Controlled Capacitance Modeling for High Definition Television

We have developed the integrated amorphous silicon gate driver circuit using the model extraction technique of the inverted staggered and nonsymmetric amorphous silicon (a-Si) thin film transistor. The relation between capacitance characteristics of hydrogenated a-Si (a-Si:H) integrated transistors and the output signal of the gate driver circuit is analyzed using UTMOST IV ver. 1.6.4.R and SMARTSPICE ver. 3.19.15.C. The accuracy of the simulated gate output signal using voltage-controlled capacitance modeling is verified with measured data. The a-Si gate driver circuit using the proposed (TFT) model increased the accuracy of rising (95.3%) and falling (92%) time, compared to the conventional model. The suggested model extraction technique can be used for bottom gate and asymmetric TFT structures.

An Integrated Amorphous Silicon Gate Driver Circuit Using Voltage-Controlled Capacitance Modeling for High Definition Television

We have developed the integrated amorphous silicon gate driver circuit using the model extraction technique of the inverted staggered and nonsymmetric amorphous silicon (a-Si) thin film transistor. The relation between capacitance characteristics of hydrogenated a-Si (a-Si:H) integrated transistors and the output signal of the gate driver circuit is analyzed using UTMOST IV ver. 1.6.4.R and SMARTSPICE ver. 3.19.15.C. The accuracy of the simulated gate output signal using voltage-controlled capacitance modeling is verified with measured data. The a-Si gate driver circuit using the proposed (TFT) model increased the accuracy of rising (95.3%) and falling (92%) time, compared to the conventional model. The suggested model extraction technique can be used for bottom gate and asymmetric TFT structures.

Analysis of temperature and wave function penetration effects in nanoscale double-gate MOSFETs

Wave function penetration has significant impact on nanoscale devices having ultrathin gate oxide. Although wave function penetration effects on ballistic drain current and capacitance-voltage characteristics in nanoscale devices have been reported in literature, to the best of the authors’ knowledge, effects of temperature on drain current incorporating with and without wave function penetration are yet to be studied. In this work, the impacts of temperature, gate dielectric and film thickness in wave function penetration on ballistic drain current of nanoscale double-gate (DG) MOSFETs are presented. The effects are observed using two-dimensional self-consistent solution of Schrödinger and Poisson equations. It has been obtained that temperature effect on drain current is greatly dependent on silicon surface orientation. Drain current of DG MOSFETs fabricated on $$\langle110\rangle$$ surface is more sensitive to temperature compared to $$\langle001\rangle$$ surface. This has been obtained for both the cases with and without incorporating wave function penetration in silicon–gate oxide interface. Electrostatics behind this phenomenon has been explained from the transmission probability of electrons from source to drain which is largely influenced by temperature on $$\langle110\rangle$$ surface compared to $$\langle001\rangle.$$ Moreover, the transmission coefficient is significantly affected by wave function penetration in $$\langle110\rangle \hbox{ than }\langle001\rangle$$ surface. Both these demonstrate greater sensitivity of temperature and wave function penetration in $$\langle110\rangle$$ silicon surface orientation compared to $$\langle001\rangle.$$ Furthermore, gate dielectric with lower conduction band offset and device scaling with thin channel thickness tend to exhibit greater impact of wave function penetration.

Unified Reaction–Diffusion Model for Accurate Prediction of Negative Bias Temperature Instability Effect

In this study, we developed a unified reaction–diffusion (R–D) model for the negative bias temperature instability (NBTI) effect over a wide range of stress times. The newly developed model provides a physics-based uniform solution and overcomes the limitations of the classical R–D models that cannot describe both the short and the long term stress regions simultaneously. In our modeling framework, the chemical reaction between inversion channel carriers and Si–H bonds at the Si/SiO2 interface dominates the short-term NBTI effects at the beginning of the stress application. Then the H2 diffusion into the polycrystalline silicon (poly-Si) gate becomes responsible for long term stress degradation. Finally, the developed R–D model is implemented into the advanced metal oxide semiconductor field effect transistor (MOSFET) model HiSIM to enable accurate circuit-aging simulation. Simulation results for the current degradation and their comparison with measurements verify the achieved high accuracy and the practical applicability of the developed NBTI model.

Unified Reaction–Diffusion Model for Accurate Prediction of Negative Bias Temperature Instability Effect

In this study, we developed a unified reaction–diffusion (R–D) model for the negative bias temperature instability (NBTI) effect over a wide range of stress times. The newly developed model provides a physics-based uniform solution and overcomes the limitations of the classical R–D models that cannot describe both the short and the long term stress regions simultaneously. In our modeling framework, the chemical reaction between inversion channel carriers and Si–H bonds at the Si/SiO2 interface dominates the short-term NBTI effects at the beginning of the stress application. Then the H2 diffusion into the polycrystalline silicon (poly-Si) gate becomes responsible for long term stress degradation. Finally, the developed R–D model is implemented into the advanced metal oxide semiconductor field effect transistor (MOSFET) model HiSIM to enable accurate circuit-aging simulation. Simulation results for the current degradation and their comparison with measurements verify the achieved high accuracy and the practical applicability of the developed NBTI model.

A new analytical subthreshold model of SRG MOSFET with analogue performance investigation

For the first time, a pseudo-two-dimensional (2D) approach is extended from a rectangular device structure to a cylindrical one. A pseudo-2D model applying Gauss's law in the cylindrical channel depletion region for undoped or lightly doped surrounding gate (SRG) silicon metal oxide semiconductor field effect transistor (MOSFETs) working in subthreshold regime is presented. From this pseudo-2D analysis, electrostatic potentials, current characteristics, the threshold voltage roll-off, the drain-induced barrier lowering and the subthreshold swing are explicitly modelled. The obtained analytical model has been extended to develop a model for transconductance-to-drain current ratio (g m/I d) in weak inversion regime. Analogue figures of merit of SRG MOSFETs are studied, including transconductance efficiency g m/I d, intrinsic gain and output resistance. The trends related to their variations along the downscaling of dimension are provided. In order to validate our model, the modelled expressions are compared with the simulated characteristics obtained from ATLAS device simulator.

Surface potential mapping of p+/n-well junction by secondary electron potential contrast with in situ nano-probe biasing

► This article investigates the surface potential of a biased p + /n-well diode. ► Inspection tool is scanning electron microscope with in situ nano-probe trigger. ► The diode depletion region and the electrical junction are identified. ► Junction profile is depicted by two-dimensional (2-D) imaging. ► The method offers high sample preparation rates in site-specific junction inspection. This article investigates the surface potential distribution of a biased p + /n-well diode using secondary electron potential contrast (SEPC) with an in situ nano-probe trigger. The SEPC image is digitized and quantified for the conversion of the image contrast to the voltage scale, allowing for the identification of the depletion region and the electrical junction. The overlap length between the poly silicon gate and the p + region is also depicted by two-dimensional (2-D) imaging. This study demonstrates that the proposed in situ nano-probe system is highly effective for surface potential mapping.

Electron detrapping in thin hafnium silicate and nitrided hafnium silicate gate dielectric stacks

The kinetics of zero-field and field-induced detrapping of electrons trapped in HfSixOy and HfSiON after positive bias stress on n+-polycrystalline silicon (polySi) gate of n-type metal-oxide-semiconductor (nMOS) capacitors are experimentally investigated. The self detrapping follows a simple logarithmic relation with time while field-induced detrapping upon reversing the stress voltage obeys a simple first-order exponential decay suggesting mono energetic shallow traps associated with tunnel emission of trapped electrons. Finally, our investigation raises questions about the validity of the widely used distributed capture cross section model of electron traps to explain the threshold voltage instability in MOS devices with hafnium silicate gate stacks.