Silicon Gate Research Articles

3-D Observation of dopant distribution at NAND flash memory floating gate using Atom probe tomography

Dopant control becomes more difficult and critical as silicon devices become smaller. We observed the dopant distribution in a thermally annealed polysilicon gate using Transmission Electron Microscopy (TEM) and Atom probe tomography (APT). Phosphorus was doped at the silicon-nitride-diffusion-barrier-layer-covered polycrystalline silicon gate. Carbon also incorporated at the gate for the enhancement of operation uniformity. The impurity distribution was observed using atom probe tomography. The carbon atoms had segregated at grain boundaries and suppressed silicon grain growth. Phosphorus atoms, on the other hand, tended to pile-up at the interface. A 1-nm-thick diffusion barrier effectively blocked P atom out-diffusion. Open image in new window

A full-range dual material gate tunnel field effect transistor drain current model considering both source and drain depletion region band-to-band tunneling

In this paper, a 2-D analytical model for the drain current of a dual material gate tunneling field-effect transistor is developed incorporating the effects of source and drain depletion regions. The model can forecast the effects of drain voltage, gate work function, oxide thickness, and silicon film thickness. The proposed model gives analytical expressions for the surface potential, electric field and the band to band generation rate which is numerically integrated to give the drain current. More importantly, our model accurately predicts the ambipolar current and the effects of drain voltage in the saturation region. A semi-empirical approach is used to model the transition from the linear to the saturation region, leading to an infinitely differentiable characteristics. The model is shown to be scalable down to a gate length of 50 nm. The model validation is carried out by a comparison with 2-D numerical simulations.

Self-aligned offset gate poly-Si TFTs using photoresist trimming technology

This paper reports a simple method of fabricating self-aligned offset gate (SAOG) polycrystalline silicon (poly-Si) thin film transistors (TFTs). The SAOG structure was formed by two key steps, i.e. an isotropic photoresist trimming and an additional gate fringe etching. The fabricated SAOG devices with this proposed method exhibit a significantly suppressed off-current increase with gate bias compared with the non-offset ones, and have identical bi-directional transfer characteristics under reversed source/drain biases. It is also shown that the performances of poly-Si TFTs with metal-induced lateral crystallization can be improved significantly by annealing in forming gas.

Analytical Threshold Voltage Modeling of Surrounding Gate Silicon Nanowire Transistors with Different Geometries

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

Synthesis of titanium nitride for self-aligned gate AlGaN/GaN heterostructure field-effect transistors.

In this study, titanium nitride (TiN) is synthesized using reactive sputtering for a self-aligned gate process. The Schottky barrier height of the TiN on n-GaN is around 0.5 to 0.6 eV and remains virtually constant with varying nitrogen ratios. As compared with the conventional Ni electrode, the TiN electrode presents a lower turn-on voltage, while its reverse leakage current is comparable with that of Ni. The results of annealing evaluation at different temperatures and duration times show that the TiN/W/Au gate stack can withstand the ohmic annealing process at 800°C for 1 or 3 min. Finally, the self-aligned TiN-gated AlGaN/GaN heterostructure field-effect transistors are obtained with good pinch-off characteristics.

Tri-Gate Graphene Nanoribbon Transistors With Transverse-Field Bandgap Modulation

The CMOS-compatible double-spacer lithography demonstrates a scalable approach to fabricate the tri-gate graphene nanoribbon (GNR) transistor with self-aligned side gates, controllable GNR width, and reduced variations in line-edge roughness and GNR width. The electrical characteristics show bandgap modulation with transverse fields and ambipolar conduction with perpendicular fields. Bandgap modulation parameters are extracted from various GNR devices, but the experimental results show lower critical fields than those in the theoretical calculation. By integrating the bandgap modulation effect into CMOS device designs, the device switching performance can be improved. The subthreshold region and ON-state characteristics are investigated by simulation with the extracted parameters to purge the parasitic effects in the present fabrication process. The extra side-gate dependence achieves drain current enhancement in both saturation and linear regions, and the decreasing bandgap by the increasing transverse field results in the sharp switching of 37 mV/decade close to the threshold voltage. This FET switching improvement can be directly used for low-power operation without sacrificing ON current. In addition, the low-linear-region resistance makes bandgap modulation a promising concept for power gating devices.

Analytical Model for Performance Comparison of a Nanoscale Dual Material Double Gate Silicon on Insulator (SOI) and Silicon on Nothing (SON) MOSFET

Analytical Model for Performance Comparison of a Nanoscale Dual Material Double Gate Silicon on Insulator (SOI) and Silicon on Nothing (SON) MOSFET

Gate Insulator for High Mobility Oxide TFT

High resolution display are considered to need oxide TFTs with higher mobility than 30 cm2/V.s and less parasitic capacitance. Until recently, many active materials for high mobility TFT such as ZITO1, AZITO2, IGO3, In rich IGZO4, and ZnON 5 have been reported. The proper device structure with less parasitic capacitance is known to be self-aligned top gate TFT. In designing high performance high mobility oxide TFT gate insulator deposition is very critical process especially in top gate TFT due to the difficulty in controlling the carrier amounts of high mobility oxide semiconductor. PECVD process of SiO2 induces not only H incorporation into the below layer but result in SiO2 with large amounts of H. O-H in dielectric layer is thought to be the origin of hole trapping site. Besides it causes negative Vth shift after annealing of TFT. Therefore it is very important to deposit SiO2gate dielectric film with less H without inducing H incorporation into the active layer.As the preliminary structure of top gate self-aligned TFT, we fabricate top gate staggered TFT with ITO as SD electrode, IGZO as active layer, SiO2 grown by PEALD at 250oC as the first gate insulator, SiO2 deposited by PECVD at 350oC as the main gate insulator, and Mo as the gate electrode.While the TFT annealed at 250oC showed the mobility, Vth, and S.S to be 35.5 cm2/V.s, 0V, and 0.27 V/dec., respectively, those annealed at 300oC were 39.9 cm2/V.s, -1V, and 0.32 V/dec., respectively. The annealing TFT at higher temperature than the deposition temperature of first gate insulator induced negative Vth shift from 0V to -1V with increase of mobility. A noteworthy is the stability behavior under positive/temperature stress. IGZO TFT annealed at 250oC showed positive Vth shift of 3.28V under 20V at 60oC for 10K seconds. Meanwhile that annealed at 300oC was shifted by 0.28V after same condition without change of S.S value.Positive shift of Vth under positive bias stress was mostly blamed on the defect generation at the interface and it can be alleviated by thermal annealing. However, we could not identify the origin of defects and curing mechanism by thermal annealing. After several investigations on the interface defects and annealing process, we suggest that the main origins of bias instability are oxygen interstitial as well as the weak bond formation at the interface from the plasma process during GI or active deposition. In addition, these defects can be cured by H passivation which can be incorporated during the annealing process. Therefore H in the adjacent film of active layer can be not only a bad player in terms of carrier generation but good player in a view point of passivation of defects in active layer and interface of oxide TFT.Reference[1] M. K. Ryu, S. Yang, S.-H. K. Park, C.-S. Hwang, and J. K. Jeong, IEEE Electron Device Letters, 31 (2), 144 (2010)[2] S. Yang, D. H. Cho, M. K. Ryu, S. H. Ko Park, C. S. Hwang, J. Jang, and J. K. Jeong, IEEE Electron Dev. Lett. 31, 144 (2010)[3] K. Ebata, S. Tomai, Y. Tsuruma, T. Iitsuka, S. Matsuzaki, and K. Yano, Applied Physics Express 5, 011102 (2012)[4] T. Arai and T. Sasaoka, SID Int. Symp. Digest Tech. Papers, 710 (2011).[5] Y. Ye, R. Lim, and J. M. White, JOURNAL OF APPLIED PHYSICS 106, 074512 (2009)

Analytical Modeling of Junctionless Surrounding Gate Silicon Nanowire Transitors

Analytical Modeling of Junctionless Surrounding Gate Silicon Nanowire Transitors

Causal self-energies for NEGF modelling of quantum nanowires

Electron-phonon scattering is shown to increase dramatically at small nanowire cross-sections so that the transport is not ballistic. Non-ballistic dissipative device modelling requires the full complexity of the non-equilibrium Green Function (NEGF) method. The role of causality in obtaining spectral sum rule-conserving approximations to the electron-phonon self-energies is demonstrated and applications given for wrap-round gate silicon nanowire field effect transistors. Causality violations give erroneous density of states and current densities.

Integration of a Piezoelectric Layer on Si FinFETs for Tunable Strained Device Applications

Earlier theoretical reports predicted that the usage of a piezoelectric stressor layer around the FinFET, i.e., the PiezoFET, offers a great potential for steep subthreshold slope devices. For the first time, we analyzed the practical realization of such PiezoFETs comprising a piezoelectric stressor layer, lead-zirconate-titanate (PZT), and aluminum-nitride (AlN) deposited on n-type silicon FinFETs. A high-piezoelectric response in the range of 100 pm/V has been obtained for the PZT PiezoFET evidencing the converse piezoelectric effect in the device. The piezoelectric response for the AlN device was much less (13 pm/V) as expected. Underlying device properties, such as subthreshold swing (SS) and low-field electron mobility have been significantly affected by the presence of the PZT stressor. A 20%-50% change in the mobility and a change in the SS (about 5 mV/decade) have been observed. The change can be attributed to the strain induced reduction of the interface trap density at the Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface. This strain is partly formed by the bias over the piezoelectric layer, which indicates the converse piezoelectric effect related tunable strain in both the silicon channel and gate oxide.

P‐12: A‐Si:H TFT Gate Driver with Shared Dual Pull‐Down Units for Large‐Sized TFT‐LCD Applications

AbstractA high reliable amorphous silicon gate driver with shared dual pull‐down units is proposed and fabricated for large‐sized TFT‐LCD applications. A special unit in the driver is designed to generate bipolar pulse bias for low‐level holding TFTs to suppress the threshold voltage shift, which achieves 40.5% and 34.8% improvement compared with conventional DC and unipolar pulse bias respectively according to measurement results.

Compact Analytical Model of Dual Material Gate Tunneling Field-Effect Transistor Using Interband Tunneling and Channel Transport

In this paper, we have developed a 2-D analytical model for surface potential and drain current for a long channel dual material gate (DMG) silicon-on-insulator (SoI) tunneling field-effect transistor (TFET). This model includes the effect of drain voltage, gate metal work function, oxide thickness, and silicon film thickness, without assuming a fully depleted channel. The proposed model also includes the effect of charge accumulation at the interface of the two gates and the variation in the tunneling volume with the applied gate voltage. The accuracy of the model is tested using 2-D numerical simulations. In comparison with the conventional TFET, the proposed model predicts that a DMGTFET provides a higher ON-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ), a better ON-state to OFF-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) ratio, and a better subthreshold slope.

Electrical characterization of high performance, liquid gated vertically stacked SiNW-based 3D FET biosensors

A 3D vertically stacked silicon nanowire (SiNW) field effect transistor featuring a high density array of fully depleted channels gated by a backgate and one or two symmetrical platinum side-gates through a liquid has been electrically characterized for their implementation into a robust biosensing system. The structures have also been characterized electrically under vacuum when completely surrounded by a thick oxide layer. When fully suspended, the SiNWs may be surrounded by a conformal high-κ gate dielectric (HfO2) or silicon dioxide. The high density array of nanowires (up to 7 or 8×20 SiNWs in the vertical and horizontal direction, respectively) provides for high drive currents (1.3mA/μm, normalized to an average NW diameter of 30nm at VSG=3V, and Vd=50mV, for a standard structure with 7×10 NWs stacked) and high chances of biomolecule interaction and detection. The use of silicon on insulator substrates with a low doped device layer significantly reduces leakage currents for excellent Ion/Ioff ratios >106 of particular importance for low power applications. When the nanowires are submerged in a liquid, they feature a gate all around architecture with improved electrostatics that provides steep subthreshold slopes (SS<75mV/dec), low drain induced barrier lowering (DIBL<20mV/V) and high transconductances (gm>10μS) while allowing for the entire surface area of the nanowire to be available for biomolecule sensing. The fabricated devices have small SiNW diameters (down to dNW∼15–30nm) in order to be fully depleted and provide also high surface to volume ratios for high sensitivities.

Comparison and Reduction of Conducted EMI in SiC JFET and Si IGBT-Based Motor Drives

This paper compares the conducted electromagnetic interference (EMI) in Si insulated gate bipolar transistor (IGBT) and silicon carbide (SiC) junction field-effect transistor (JFET) based motor drives. Two inverters, with the SiC and Si transistors, respectively, are built using the same circuit layout and investigated accordingly. Their conducted EMI levels are compared under the conditions of without filter and with traditional common mode (CM) filters. Reasons of the exhibited different noise emissions are analyzed. To verify the discussions, two inverters are tested in the CM. This allows for the identification and analysis of their maximized CM and differential mode (DM) wave shapes. It is shown that the excited parasitic oscillations during the switching transients are magnified more in the SiC JFET inverter, which is the main cause of the noise difference. Lastly, improved filtering solutions are proposed, which effectively suppressed the increased high-frequency noise due to the faster SiC switching speed.

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (Vt) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal–oxide–nitride–oxide–silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si–oxide–nitride–oxide–silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial Vt roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (Lg) is scaled down to 46 nm or less.

Analytical modeling and simulation of germanium single gate silicon on insulator TFET

This paper proposes a new two dimensional (2D) analytical model for a germanium (Ge) single gate silicon-on-insulator tunnel field effect transistor (SG SOI TFET). The parabolic approximation technique is used to solve the 2D Poisson equation with suitable boundary conditions and analytical expressions are derived for the surface potential, the electric field along the channel and the vertical electric field. The device output tunnelling current is derived further by using the electric fields. The results show that Ge based TFETs have significant improvements in on-current characteristics. The effectiveness of the proposed model has been verified by comparing the analytical model results with the technology computer aided design (TCAD) simulation results and also comparing them with results from a silicon based TFET.

Positive bias temperature instability in p-type metal-oxide-semiconductor devices with HfSiON/SiO2 gate dielectrics

We present a detailed investigation on positive-bias temperature stress (PBTS) induced degradation of nitrided hafnium silicate (HfSiON)/SiO2 gate stack in n+-poly crystalline silicon (polySi) gate p-type metal-oxide-semiconductor (pMOS) devices. The measurement results indicate that gate dielectric degradation is a composite effect of electron trapping in as-fabricated as well as newly generated neutral traps, resulting a significant amount of stress-induced leakage current and generation of surface states at the Si/SiO2 interface. Although, a significant amount of interface states are created during PBTS, the threshold voltage (VT) instability of the HfSiON based pMOS devices is primarily caused by electron trapping and detrapping. It is also shown that PBTS creates both acceptor- and donor-like interface traps via different depassivation mechanisms of the Si3 ≡ SiH bonds at the Si/SiO2 interface in pMOS devices. However, the number of donor-like interface traps ΔNitD is significantly greater than that of acceptor-like interface traps ΔNAit, resulting the PBTS induced net interface traps as donor-like.

Thin-Film Heterojunction Field-Effect Transistors With Crystalline Si Channels and Low-Temperature PECVD Contacts

Heterojunction field-effect transistor devices with thin-film crystalline silicon channels and gate, source, and drain contacts formed by plasma-enhanced chemical vapor deposition (PECVD) at temperatures <;200 °C have been demonstrated. The gate and source/drain contacts are comprised of hydrogenated amorphous silicon and crystalline silicon, respectively; both grown in the same PECVD reactor. An ON/OFF ratio of >106, pinch-off voltage of approximately -0.6 V, turn-on slope of ~70 mV/decade, and off-current of ~25 fA/μm have been achieved at process temperatures <;200 °C.

Influence of Si Surface Roughness on Electrical Characteristics of MOSFET with HfON Gate Insulator Formed by ECR Plasma Sputtering

To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon (Si) should be realized. In this paper, the influence of Si surface roughness on electrical characteristics of MOSFET with hafnium oxynitride (HfON) gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering was investigated for the first time. The surface roughness of Si substrate was reduced by Ar/4.9%H2 annealing utilizing conventional rapid thermal annealing (RTA) system. The obtained root-mean-square (RMS) roughness was 0.07nm (without annealed: 0.18nm). The HfON was formed by 2nm-thick HfN deposition followed by the Ar/O2 plasma oxidation. The electrical properties of HfON gate insulator were improved by reducing Si surface roughness. It was found that the current drivability of fabricated nMOSFETs was remarkably increased by reducing Si surface roughness. Furthermore, the reduction of Si surface roughness also leads to decrease of the 1/f noise.