Silicon Gate Research Articles

Effect of weak metallic contamination on silicon epitaxial layer and gate oxide integrity

AbstractThe detection of metallic contaminants in microelectronics devices is one of the main issues in production line. In fact they could diffuse rapidly into the silicon bulk and establishing energy states into the silicon energy‐band gap. The presence of trace of metals on the silicon surface can also degrade the gate oxide integrity, cause structural defect in silicon epitaxial layers or anomalies in silicon/gate oxide interface. Usually in semiconductor manufacturing superficial metallic contamination is monitored using Total X‐ray Reflection Fluorescence spectroscopy (TXRF) and performing specific electrical measurements on dedicated capacitor. In this work a weak contamination, undetected by TXRF analysis, was revealed by Transmission Electron Microscopy (TEM) observing lattice damaging and Time of Flight Secondary Ion Mass Spectrometry (ToF‐SIMS) detecting an anomalous Na distribution in depth profile. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Experimental Study of Physical-Vapor-Deposited Titanium Nitride Gate with An n+-Polycrystalline Silicon Capping Layer and Its Application to 20 nm Fin-Type Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors

We have comparatively investigated the electrical characteristics including threshold voltage (Vth) variability and mobility by fabricating n+-polycrystalline silicon (poly-Si) gate and physical-vapor-deposited (PVD) titanium nitride (TiN) gate fin-type double-gate metal–oxide–semiconductor field-effect transistors (FinFETs), and demonstrated 20-nm-thick PVD-TiN gate FinFETs with a symmetrical Vth. It is experimentally found that the gate stack of a 20-nm-thick PVD-TiN layer capped with a 100-nm-thick n+-poly-Si layer is very effective for setting a symmetrical Vth for undoped FinFETs keeping almost the same Vth variability and mobility as those in the case of the n+-poly-Si gate only. On the other hand, mobility degradation was observed in the case of pure 50-nm-thick PVD-TiN gates. These results indicate that mobility degradation probably caused by the thick metal gate induced mechanical stress can be effectively suppressed by reducing the PVD-TiN thickness to 20 nm or less.

Silicon Carbide Vertical JFET with Self-Aligned Nickel Silicide Contacts

Trenched implanted vertical JFETs (TI-VJFETs) with self-aligned gate and source contacts were fabricated on commercial 4H-SiC epitaxial wafers. Gate regions were formed by aluminium implantation through the same silicon oxide mask which was used for etching mesa-structures. Self-aligned nickel silicide source and gate contacts were formed using a silicon oxide spacer formed on mesa-structure sidewalls by anisotropic thermal oxidation of silicon carbide followed by anisotropic reactive ion etching of oxide. Fabricated normally-on 4H-SiC TI-VJFETs demonstrated low gate leakage currents and blocking voltages exceeding 200 V.

Dummy Poly Silicon Gate Removal by Wet Chemical Etching

For the gate last integration scheme, dummy poly silicon gate removal is one of the indispensable processes either for a high-k first or a high-k last route. In this paper, experimental results of dummy poly silicon gate removal using TetraMethyl Ammonium Hydroxide (TMAH) chemical etching are presented. The preliminary results show that the poly silicon removal rate was highly sensitive to the wet etch conditions. By optimizing the wet etch conditions, high selectivity of poly silicon with respect to SiO2, Si3N4 and hafnium silicon oxynitride (HfSiON) was obtained. A gate trench of critical dimension (CD) of about 70 nm without poly silicon residue was fabricated using optimized conditions. The excellent etch capability of the optimized wet etch process was also demonstrated by controlling trench profiles.

Nanosecond pulsed field emission from single-gate metallic field emitter arrays fabricated by molding

Electrically gated pulsed field emission from molybdenum field emitter arrays was studied. Single-gate field emitter array devices supported by metallic substrates were fabricated by a combination of molding and a self-aligned gate process. Devices were tested in a low-inductance cathode holder compatible with the high-acceleration electric field of a pulsed diode gun. Pulsed field emission down to 1.1 ns was observed for single-gate devices with 1.2×103–1.2×105 emitter tips with 5 μm array pitches. Integrating the field emitter arrays in a high-voltage pulsed diode gun, the authors demonstrated nanosecond field emission at an acceleration field of 30 MV/m at the cathode surface and acceleration of the field emission electron beam up to 300 keV. In addition, transverse beam emittance of the single-gate devices was measured with two different array sizes.

Fabrication of sub-100-nm metal-oxide-semiconductor field-effect transistors with asymmetrical source/drain using I-line double patterning technique

The authors present a simple double patterning technique with I-line stepper to define nanoscale structures and have successfully fabricated n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with sub-100-nm gate length. With this approach, polycrystalline silicon (poly-Si) gate with linewidth down to 80 nm could be formed with good control, which far exceeds the resolution limit of conventional I-line lithography. Moreover, ineffectiveness of end point detection in the second poly-Si gate definition is also addressed. For reliable process control in the second etching step, appropriate mask design is found to be essential. Finally, sub-100-nm MOSFETs with or without halo implemented symmetrically or asymmetrically are fabricated and characterized.

Design of Bidirectional and Highly Stable Integrated Hydrogenated Amorphous Silicon Gate Driver Circuits

Based on the use of a standard five-mask process, this work presents a new integrated hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) gate driver circuit for large size TFT-LCD applications, composed of a pull-up circuit with three TFTs, a pull-down circuit with ten TFTs, and two capacitors. The pull-up circuit, which separates the row line from the carry signal, prevents distortion of the output pulse. Moreover, the pull-down circuit with the AC-driving method can reduce the threshold voltage shift ( shift) to stabilize the output voltage and suppress the fluctuation of the row line, subsequently increasing the operating lifetime. According to accelerated lifetime test results, this gate driver circuit operates stably over 240 hours at 100°C. Additionally, the scan direction of the proposed circuit can be modified using two control signals and applied to the reversal display of an image.

Etch mechanisms of silicon gate structures patterned in SF6/CH2F2/Ar inductively coupled plasmas

Patterning complex metal gate stack becomes increasingly challenging since the gate dimension for all isolated as well as dense gate structures present on 300 mm wafer needs to be controlled within the nanometer range. In this article, the authors show that SF6/CH2F2/Ar plasma chemistries to etch the polysilicon gate present very interesting critical dimension (CD) control capabilities for advanced gate etch strategies compared to commonly used HBr/O2/Cl2 plasma chemistries, thanks to the different mechanisms involved in the passivation layer formation on the gate sidewalls. Indeed, contrary to HBr/Cl2/O2 plasma chemistries, the passivation layers in SF6/Ar/CH2F2 plasmas are not formed from deposition of etch by-products coming from the gas phase but the passivating species are chemically sputtered from the bottom of the etched structures and coat the silicon sidewalls by line of sight deposition. Such mechanisms result in thin and uniform CFX passivation layers on the gate sidewalls very similar in dense and isolated structures leading to an improved CD control.

Deconvoluted Si 2p Photoelectron Spectra of Ultra thin SiO2 film with FitXPS method

The main impetus for our research is provided by the growing interest worldwide in ultra thin silicon dioxide on silicon based nano devices. The obvious need for better knowledge in the ultra thin gate silicon dioxides, is motivated both by interests in fundamental research and phenomenology as well as by interests in possible applications, which can be found with better fitting of experimental spectra. The up – and down- spin roles are considered for studying the nano structural properties of bulk, interface and surface states of ultra thin film, down to 2 nm and also appealing to the field of surface science. The obtained results show the above states can be determined and distinguished with spin orientations in FitXPS method.

Nanometer-Scale Oxide Thin Film Transistor with Potential for High-Density Image Sensor Applications

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

Scalable Synthesis of Graphene on Patterned Ni and Transfer

We present an approach to mass produce high-quality graphene on insulator substrate. Ni dots with single or few grains were achieved by annealing. Electron backscattered diffraction indicated that almost all of the Ni dots had (111) surface that is parallel to the substrate. Single-layer graphene with good crystalline quality has been grown on Ni dots. The patterned graphene films were transferred to insulating substrates by wafer bonding and etch back technique, which resulted in zero misalignment, low contamination, and high yield (>90%). Graphene-based field-effect transistors with self-aligned gate were fabricated with this method, which demonstrate the potential of this method as a candidate for mass production of graphene transistors.

Effect of an Ultrathin SiN Cap Layer on the Bias Temperature Instability in Metal–Oxide–Semiconductor Field-Effect Transistors with HfSiON Gate Stacks

The negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) of HfSiON/SiO2 metal–oxide–semiconductor field-effect transistors (MOSFETs) with and without an ultrathin SiN cap layer were investigated. For the PBTI of n-channel MOSFETs, the dominant degradation mechanism is the electron tunneling from the Si channel and electron trapping in the pre-existing traps in HfSiON. The SiN cap layer does not make a significant difference in PBTI. For the NBTI of p-channel MOSFETs, on the other hand, both the electron trapping in HfSiON and the dissociation of Si–H bonds at the SiO2/channel-Si interface (i.e., the interface trap generation) play a role and the SiN cap layer makes a significant difference in NBTI: the dominant degradation mechanism for the devices without the SiN cap layer is the electron trapping in HfSiON, whereas that for the devices with the SiN cap layer is the interface trap generation. This indicates that the interfacial SiN cap layer can effectively suppress the electron tunneling from the polycrystalline silicon (polySi) gate to HfSiON under the NBT stress.

Threshold Voltage Increasing Induced by Poly Silicon Gate Counter Pre-Doping in NMOSFET

PMOS poly Si gate blank pre-doping combined with NMOS poly Si counter pre-doping process scheme is demonstrated to keep the benefit of one photolithography saving while no device or product properties degradation.

Recent Progress of Ferroelectric-Gate Field-Effect Transistors and Applications to Nonvolatile Logic and FeNAND Flash Memory

We have investigated ferroelectric-gate field-effect transistors (FeFETs) with Pt/SrBi2Ta2O9/(HfO2)x(Al2O3)1−x (Hf-Al-O) and Pt/SrBi2Ta2O9/HfO2 gate stacks. The fabricated FeFETs have excellent data retention characteristics: The drain current ratio between the on- and off-states of a FeFET was more than 2 × 106 after 12 days, and the decreasing rate of this ratio was so small that the extrapolated drain current ratio after 10 years is larger than 1 × 105. A fabricated self-aligned gate Pt/SrBi2Ta2O9/Hf-Al-O/Si FET revealed a sufficiently large drain current ratio of 2.4 × 105 after 33.5 day, which is 6.5 × 104 after 10 years by extrapolation. The developed FeFETs also revealed stable retention characteristics at an elevated temperature up to 120 °C and had small transistor threshold voltage (Vth) distribution. The Vth can be adjusted by controlling channel impurity densities for both n-channel and p-channel FeFETs. These performances are now suitable to integrated circuit application with nonvolatile functions. Fundamental properties for the applications to ferroelectric-CMOS nonvolatile logic-circuits and to ferroelectric-NAND flash memories are demonstrated.

An Analytical $I$– $V$ Model for Surrounding-Gate Transistors That Includes Quantum and Velocity Overshoot Effects

A new analytical model is presented for the inversion charge of surrounding-gate transistors (SGTs). Quantum effects are taken into account by means of a modified capacitance model that includes the inversion charge centroid and a correction to the threshold voltage. A drain current model for the SGT that includes velocity saturation, short channel, and velocity overshoot effects is also developed. The model accurately reproduces both simulated and experimental results for different silicon core radii and gate voltages.

Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory

In this paper, arch gate silicon–oxide–nitride–oxide–silicon (SONOS) flash memory is studied. The key technology for this device lies in making the device channel on an arch-shaped silicon fin. This feature enhances the electric field across the tunneling oxide by field concentration, and at the same time, reduces the field across the barrier oxide. Thus, when the high gate voltage is applied in the program operation, the tunneling current, and in turn, the program speed is drastically improved. The lowered electric field at the top oxide prohibits the electron back-tunneling from the polycrystalline silicon gate, which enables more reliable and faster erase operation. Full fabrication processes and the measurement results are presented in detail. The process and device simulation results are also given to confirm the critical electrostatic characteristics of the Arch SONOS flash memory device at each step and design the process integration.

Low damage fully self-aligned replacement gate process for fabricating deep sub-100 nm gate length GaAs metal-oxide-semiconductor field-effect transistors

This article describes a process flow which has enabled the first demonstration of functional, fully self-aligned, 40 nm gate length replacement gate enhancement mode GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) with GaxGdyOz as high-κ dielectric, Pt/Au metal gate stack, and SiN sidewall spacers. The flow uses blanket metal and dielectric deposition and low damage dry etch modules. As a consequence, no critical dimension lift-off processes are required. As a gate replacement approach has been developed, the process is suitable for easily incorporating different gate metals, opening the way to work function engineering to control threshold voltage and so is a significant step forward to the demonstration of high performance “siliconlike” III-V MOSFETs.

(Invited) Nanocrystalline Silicon Thin Film Transistors

We review performance characteristics of top- and bottom-gate nanocrystalline silicon (nc-Si) thin film transistors (TFTs). Top gate TFTs with nc-Si active layer of nearly 80% crystallinity along with a silicon oxide gate dielectric produce high electron mobilities; values two orders higher than the amorphous silicon counterpart. In contrast, bottom-gate TFTs with silicon nitride gate dielectric and nc-Si active layer of similar crystallinity yield a mobility that is only marginally better than amorphous silicon TFT. However, they are highly stable with no visible presence of defect state creation in the active layer. In contrast, top-gate TFTs suffer from severe charge trapping in the low quality oxide gate dielectric.

Solution-Processed Oxide Thin Film Transistors with Indium Zinc Tin Oxide Semiconductor: Nitrogen Effect

Thin film transistors (TFTs) with nitrogen incorporated indium zinc tin oxide (IZTO:N) channel layer were fabricated and characterized. For the IZTO:N channel, TFTs was fabricated on heavily doped Si as a common gate electrode and silicon nitride (SiNx) was used as a gate dielectric layer. The IZTO:N layer was formed by spin-coating as precursor type solution and annealed at 600C. The precursors for indium, zinc, and tin were indium chloride, zinc chloride, and tin chloride. The incorporation of nitrogen was accomplished by addition of NH4OH solution. The IZTO:N TFT prepared with the precursor solution having 0.7% NH4OH has show the performance in mobility 1.2cm2/Vs, Ion/off of 10^6 and threshold voltage of 8.5V.

(Invited) Germanium on Sapphire Technology

Silicon-on-sapphire (SOS) substrates have been proven to offer significant advantages in the integration of passive and active devices in RF circuits. Germanium on insulator technology is a candidate for future higher performance circuits. Thus the advantages of employing a low loss dielectric substrate other than a silicon-dioxide layer on silicon will be even greater. This paper covers the production of germanium on sapphire (GeOS) substrates by wafer bonding. The quality of the germanium back interface is studied and a tungsten self-aligned gate process MOST process has been developed. High low field mobilities of 450-500 cm2/V-s have been achieved for p-channel MOSTs produced on GeOS substrates. Thick germanium on alumina (GOAL) substrates have also been produced.