Abstract
We have developed the integrated amorphous silicon gate driver circuit using the model extraction technique of the inverted staggered and nonsymmetric amorphous silicon (a-Si) thin film transistor. The relation between capacitance characteristics of hydrogenated a-Si (a-Si:H) integrated transistors and the output signal of the gate driver circuit is analyzed using UTMOST IV ver. 1.6.4.R and SMARTSPICE ver. 3.19.15.C. The accuracy of the simulated gate output signal using voltage-controlled capacitance modeling is verified with measured data. The a-Si gate driver circuit using the proposed (TFT) model increased the accuracy of rising (95.3%) and falling (92%) time, compared to the conventional model. The suggested model extraction technique can be used for bottom gate and asymmetric TFT structures.
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