SiGe Virtual Substrates Research Articles

An efficient wet-cleaning of SiGe virtual substrates and of thick, pure Ge layers on Si(0 0 1) after a chemical mechanical planarization step

The aim of this study is to propose an efficient wet cleaning of the surfaces of the SiGe virtual substrates just after a chemical mechanical polishing step. We have first of all studied the chemical compatibility of miscellaneous solutions, such as the standard cleaning 1 (SC1), the Standard Cleaning 2 (SC2), the CARO one etc with SiGe. A definite, logarithmic-like increase of the etch rate with the Ge content has been obtained for the SC1, the SC2 and the CARO solutions (with values 1000–10,000 those of Si evidenced for pure Ge), making them unsuitable for Ge contents above 30%. We have thus investigated the efficiency of new cleaning sequences (named “DDC-SiGe” for SiGe and “HF/O 3” for pure Ge) that call upon diluted HF and ozone solutions spiked with HCl, on SiGe and pure Ge. The overall material consumption of those cleaning sequences, which increases from 10 Å for pure Si up to 130 Å for pure Ge, is quite low. The particle removal efficiency of such cleanings is around 99% for Si 0.8Ge 0.2 and Si 0.7Ge 0.3. It drops down to 83% for Si 0.5Ge 0.5 and to 65% for pure Ge. This is most probably due to pre-existing epitaxy defects which are revealed during the wet cleaning then wrongly assimilated to particles by our surface inspection tool. The metallic contaminants present on the surface after the use of our wet cleaning sequences have a surface density lower than 10 10 atoms cm −2, this whatever the Ge content of the underlying layer.

Direct regrowth of thin strained silicon films on planarized relaxed silicon–germanium virtual substrates

We discuss a method for fabricating strained Si layers via deposition directly onto planarized relaxed SiGe virtual substrates, a process termed direct regrowth (DRG). We show that a trade-off exists between surface roughness and cleanliness of the Si/SiGe interface. Using this knowledge, we discuss process requirements to ensure that strained Si wafers produced via direct regrowth are free of interfacial contamination, exhibit ultra-low surface roughness, and feature abrupt Si/SiGe interfacial transitions. Finally, we show that metal-oxide-semiconductor field-effect transistors produced on strained Si channels fabricated via direct regrowth exhibit excellent device performance, suggesting the viability of the DRG process for manufacture of high quality strained Si wafers.

Fabrication of strained-Si channel p-MOSFET’s on ultra-thin SiGe virtual substrates

In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/100nm Low Temperature Si (LT-Si)/10nm Si buffer was grown by Molecular Beam Epitaxy (MBE), in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET’s (L-4.2 μm) transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.

Optimized measurement of strained Si thickness and SiGe virtual substrate composition by spectroscopic ellipsometry

Optimized parameters for measuring strained Si wafers by spectroscopic ellipsometry (SE) are presented. It is shown that SE sensitivity to the main wafer characteristics of interest–native SiO 2 thickness, strained Si thickness, and composition of the underlying fully relaxed SiGe virtual substrate–is optimized for an incident angle of ∼78° and an energy (wavelength) range of ∼2.5–3.6 eV (∼350–500 nm). A series of 20 strained Si samples with thickness ranging from 10 to 26 nm were grown on either Si 0.81Ge 0.19 or Si 0.85Ge 0.15 virtual substrates and measured by SE using the optimized parameters. To enable accurate data fits the complex refractive index of strained Si was experimentally obtained and is presented, and justification is provided for ignoring the expected birefringence. Excellent agreement is demonstrated between strained Si thickness measurements made by SE and grazing incidence X-ray reflectivity. Good agreement was also obtained between the underlying SiGe virtual substrate composition measured by SE and that measured by highly accurate {224} reciprocal space X-ray diffraction maps. These results establish the suitability of SE as a measurement technique for strained Si wafers.

Ge out-diffusion and its Effect on Electrical Properties in s-Si/SiGe Devices

AbstractIn this paper we report on the quantification of Ge diffusion in strained Si/SiGe (s-Si/SiGe) structures for different Ge content in the SiGe virtual substrate. Using TCAD tools, the diffusivity has been calculated by varying pre-exponential factor and activation energy for Ge diffusion in s-Si and SiGe layers separately and obtaining a fit to the SIMS profiles. We observe an exponential and a linear dependence of pre-factor and activation energy for Ge diffusion in s-Si and SiGe, respectively, which is in agreement with literature. As a result of diffusion, the carrier confinement in thin strained layer reduces and the mobility is affected. Using C-V measurements on MOS capacitors fabricated along with devices, a shift in the flat band voltage has been observed and is attributed to a change in the interface trapped and fixed oxide charge. We observe a stronger effect of the variation of strained layer thickness than Ge content on the change in the flatband voltage. This observation is consistent with an exponential increase in Ge arriving at the interface with decrease in strained layer thickness.

The CMP Process and Cleaning Solution for Planarization of Strain-Relaxed SiGe Virtual Substrates in MOSFET Applications

The effects of different polishing pads and slurry solid contents on the SiGe chemical mechanical polish (CMP) process were investigated. By optimizing the polishing conditions, a smooth strained-Si surface on a flattened buffer layer of can be achieved. The novel cleaning solutions with various surfactants and chelating agents for post-CMP SiGe were studied. There was about 10% current enhancement of the optimal cleaning conditions, showing high performance in particle removal, metallic cleaning, and electrical characteristics.

Growth of strained Si on He ion implanted Si/SiGe heterostructures

He ion implantation into Si/SiGe heterostructures and annealing are used to produce strain-relaxed SiGe layers and simultaneously thin strained Si layers. In addition we present various studies of subsequent epitaxial overgrowth by chemical vapor deposition. Up to a thickness of 8 nm strained Si on relaxed SiGe virtual substrates are made by strain transfer via dislocation propagation. An initial cubic-Si/strained-SiGe/Si(1 0 0) structure is transformed by He + ion implantation and annealing into strained-Si/partially relaxed-SiGe/Si(1 0 0). These layers show low threading dislocation densities and very smooth surfaces. Such virtual substrates were overgrown with Si to achieve 20 nm of strained Si. A tensile strain of 0.8% was measured by Raman spectroscopy for an 18.5 nm sSi layer with a surface roughness of only 0.8 nm measured by AFM. The threading dislocation density was reduced by overgrowth of an additional strain adjusted SiGe layer and sSi layer.

Low-temperature molecular beam epitaxy growth of Si/SiGe THz quantum cascade structures on virtual substrates

Si/SiGe quantum cascade structures containing superlattice up to 100 periods have been grown on SiGe virtual substrates by using solid-source molecular beam epitaxy at low temperature. The surface morphology and structural properties of the grown samples were characterized using various experimental techniques. It has been concluded that the structures were completely symmetrically strained with high crystalline quality, precise layer parameters, and excellent reproducibility. Electroluminescence was observed with peaked intensity at ∼3 THz at both 4 and 40 K, which agrees very well with expected interwell intersubband transition according to the design.

The use of Raman spectroscopy to identify strain and strain relaxation in strained Si/SiGe structures

Strained silicon/SiGe alloy films have attracted interest in recent years because of their importance for high-speed microelectronic devices. In order to achieve such speed increases, devices are made from silicon with a tensile strain introduced by epitaxial deposition onto a SiGe alloy with a larger lattice parameter. In this study, strained silicon layers grown on SiGe virtual substrates have been investigated by Raman spectroscopy to determine their strain and if any strain relaxation has occurred. The Raman spectra of epitaxial Si 1− x Ge x alloys ( x = 0.1, 0.15…0.3) covered with a thin (∼ 10 nm) Si cap layer were analyzed with the aim of accurately measuring the Si cap peak position which is related to macrostrain. However, the signal obtained from the Si cap layer is very weak and shows considerable overlap with the Si in SiGe peak. In order to find the Si cap peak position, two methods were performed. The first method is to obtain a difference spectrum before and after selectively etching the Si cap and the second method involves peak-fitting and deconvolution by software. Both of these methods show very good agreement, however the peak fitting technique is a faster and non-destructive technique and is suitable for analyzing devices at various stages of processing. The generation of strain as a function of germanium content of the virtual substrate and the relaxation of this strain at defects such as dislocations is discussed.

Mobility-limiting mechanisms in single and dual channel strained Si/SiGe MOSFETs

Dual channel strained Si/SiGe CMOS architectures currently receive great attention due to maximum performance benefits being predicted for both n- and p-channel MOSFETs. Epitaxial growth of a compressively strained SiGe layer followed by tensile strained Si can create a high mobility buried hole channel and a high mobility surface electron channel on a single relaxed SiGe virtual substrate. However, dual channel n-MOSFETs fabricated using a high thermal budget exhibit compromised mobility enhancements compared with single channel devices, in which both electron and hole channels form in strained Si. This paper investigates the mobility-limiting mechanisms of dual channel structures. The first evidence of increased interface roughness due to the introduction of compressively strained SiGe below the tensile strained Si channel is presented. Interface corrugations degrade electron mobility in the strained Si. Roughness measurements have been carried out using AFM and TEM. Filtering AFM images allowed roughness at wavelengths pertinent to carrier transport to be studied and the results are in agreement with electrical data. Furthermore, the first comparison of strain measurements in the surface channels of single and dual channel architectures is presented. Raman spectroscopy has been used to study channel strain both before and after processing and indicates that there is no impact of the buried SiGe layer on surface macrostrain. The results provide further evidence that the improved performance of the single channel devices fabricated using a high thermal budget arises from improved surface roughness and reduced Ge diffusion into the Si channel.

SiGe virtual substrates growth up to 50% Ge concentration for Si/Ge dual channel epitaxy

We have grown in reduced pressure–chemical vapor deposition (RP-CVD) SiGe virtual substrates with Ge concentrations ranging from 20 up to 50%. We have observed an increase of the surface rms roughness with the final Ge content of the virtual substrates. Cross sectional transmission electron microscopy images revealed an effective confinement of the misfit dislocations inside the graded buffer. The final Ge content of the virtual substrate has no impact on the field threading dislocations density, whereas an increase of the pile-up threading dislocations density occurred. We have then used Si 0.49Ge 0.51 virtual substrates as templates for the growth of Si/Ge dual channels. Although some dislocations were observed, mainly in the silicon layer, we have demonstrated the growth feasibility of such highly mismatched heterostructures in RP-CVD.

Smoothing of Si0.7Ge0.3 virtual substrates by gas-cluster-ion beam

The planarization of the SiGe virtual substrate surface is crucial for the fabrication of high-performance strained-Si metal-oxide-semiconductor field-effect transistors. In this letter, we report on the smoothing of the inherently crosshatched rough surfaces of SiGe deposited by molecular beam epitaxy on Si substrates by gas cluster ion beams. Atomic force microscopy measurements show that the average surface roughness (Ra) of the SiGe layer could be reduced considerably from 3.2 to 0.7 nm without any crosshatched pattern. Rutherford backscattering in combination with channeling was used to study the damage produced by cluster bombardment. No visible surface damage was observed for the normal-incidence smoothed SiGe with postsmoothing glancing angle cluster ion beam etching.

High germanium content SiGe virtual substrates grown at high temperatures

We have grown high Ge content SiGe virtual substrates at high temperatures in a reduced pressure–chemical vapour deposition reactor. We have notably focused on the effects of growth temperature and final germanium content on the virtual substrates’ structural properties (macroscopic degree of strain relaxation, surface roughness and threading dislocation densities). Increasing the growth temperature of Si 0.80Ge 0.20 virtual substrates leads to a severe reduction of both the field and pile-up threading dislocation densities, while keeping a relatively smooth cross-hatched surface. A growth temperature of 950 °C allows one to achieve a 10 5 cm −2 (10 4 cm −2) field (pile-up) threading dislocations density. For a fixed growth temperature, increasing the germanium content of virtual substrates leads to an increase of the surface roughness that is more severe at 900 than at 850 °C. The final Ge content (between 20% and 50%) has little impact on the field threading dislocation density, whereas it does increase the pile-up threading dislocation density. Such an increase seems to be influenced by the surface roughness.

Impact of dislocation densities on n+∕p and p+∕n junction GaAs diodes and solar cells on SiGe virtual substrates

Recent experimental measurements have shown that in GaAs with elevated threading dislocation densities (TDDs) the electron lifetime is much lower than the hole lifetime [C. L. Andre, J. J. Boeckl, D. M. Wilt, A. J. Pitera, M. L. Lee, E. A. Fitzgerald, B. M. Keyes, and S. A. Ringel, Appl. Phys. Lett. 84, 3884 (2004)]. This lower electron lifetime suggests an increase in depletion region recombination and thus in the reverse saturation current (J0 for an n+∕p diode compared with a p+∕n diode at a given TDD. To confirm this, GaAs diodes of both polarities were grown on compositionally graded Ge∕Si1−xGex∕Si (SiGe) substrates with a TDD of 1×106cm−2. It is shown that the ratio of measured J0 values is consistent with the inverse ratio of the expected lifetimes. Using a TDD-dependent lifetime in solar cell current–voltage models we found that the Voc, for a given short-circuit current, also exhibits a poorer TDD tolerance for GaAs n+∕p solar cells compared with GaAs p+∕n solar cells. Experimentally, the open-circuit voltage (Voc) for the n+∕p GaAs solar cell grown on a SiGe substrate with a TDD of ∼1×106cm−2 was ∼880mV which was significantly lower than the ∼980mV measured for a p+∕n GaAs solar cell grown on SiGe at the same TDD and was consistent with the solar cell modeling results reported in this paper. We conclude that p+∕n polarity GaAs junctions demonstrate superior dislocation tolerance than n+∕p configured GaAs junctions, which is important for optimization of lattice-mismatched III–V devices.

Study of strain relaxation in Si/SiGe metal-oxide-semiconductor field-effect transistors

We report a study of strained Si metal-oxide-semiconductor field-effect transistors (MOSFET’s) fabricated using a high thermal budget. The impact of Si channel strain on MOSFET performance, leakage current, and yield is investigated for Si1−xGex virtual substrates having Ge compositions varying from 0% to 30%. Increasing the Ge fraction in the SiGe virtual substrate increases the amount of tensile strain in the Si layer and consequently increases the electron mobility. High levels of strain, however, reduce the critical thickness of strained Si, above which Si becomes metastable and susceptible to relaxation during high-temperature device fabrication. Increasing the Ge composition in the virtual substrate up to 30% is shown to result in significant enhancements in MOSFET drain current and transconductance due to increased strain in the device channels. However, cross-wafer electrical yield data as a function of Ge composition are reported and show that increasing Ge compositions above 15% simultaneously reduces device yield. Off-state leakage current and gate oxide interface trap density are also shown to increase significantly when the Ge content in the virtual substrate is raised above 25%. Trade-offs between device performance and wafer yield are thus presented. The results identify the appropriate parameter window for virtual substrate Ge composition if acceptable MOSFET on-state performance, off-state performance, device yield, and reliability are to be achieved using a high thermal budget process. Detailed physical and electrical analyses have been carried out in order to understand the causes of the degraded performance for high Ge content virtual substrates. The reduction in yield with increasing Ge composition is shown to be related to a combination of strain relaxation and as-grown material quality. The strain state has been studied using Raman spectroscopy, Schimmel etching, and transmission electron microscopy, in conjunction with electrical measurements. The ability of techniques commonly used to assess strain relaxation is critically examined. The degraded electrical performance for strained Si/Si0.70Ge0.30 devices is shown to correlate well with the presence of surface threading dislocations resulting from strain relaxation. The relative effects of as-grown material quality and strain relaxation on device performance have also been investigated. The impact of device operating conditions on performance enhancements has further been analyzed and implications for the design of both n- and p-channel strained Si/SiGe MOSFET’s are discussed.

Thin relaxed SiGe virtual substrates grown by low-energy plasma-enhanced chemical vapor deposition

We present a method to produce thin SiGe virtual substrates suitable for electronic applications. This method is based on the gas phase process of low-energy plasma-enhanced chemical vapor deposition. The strain-relaxed buffers are characterized by X-ray diffractometry, transmission electron microscopy and atomic force microscopy. We find threading dislocation densities lower than 3×10 8 cm −2 and a surface rms roughness of 1.8 nm, for a buffer thickness of 500 nm. Room temperature electrical results are also presented, which are competitive with those obtained on SiGe buffers produced by other methods.

Inhomogeneous distribution of dislocations in a SiGe graded layer and its influence on surface morphology and misfit dislocations at the interface of strained Si∕Si0.8Ge0.2

To improve the quality of a strained Si layer on a SiGe virtual substrate, the distribution of dislocations in a graded SiGe layer is characterized using electron beam induced current (EBIC). A crosshatch pattern of dark and bright bands running along the two ⟨110⟩ directions is observed in an EBIC image taken with a 25-keV-electron beam at 80 K. These dark and bright EBIC bands are attributed, respectively, to high- and low-density dislocation regions in the graded SiGe layer, as is confirmed by transmission electron microscopy. The effects of such an inhomogeneous dislocation distribution on the surface morphology and the generation of misfit dislocations (MDs) at the interface of strained Si∕SiGe are investigated. Comparison between the EBIC image and an atomic force microscope image shows that the high-density dislocation regions are correlated with ridges on the surface topography. A chemical etching image shows that most of the MDs lie along the edges of surface ridges. Possible mechanisms of MD generation at the interface of the strained Si∕SiGe are proposed.

SiGe quantum cascade structures for light emitting devices

The realisation of III–V quantum cascade lasers has initiated a strong interest in developing a Si/SiGe-based quantum cascade laser over the last 3 years. Most efforts were focused on the growth of strain-balanced Si/SiGe superlattices on strain-relaxed SiGe virtual substrates. This paper discusses the progress so far and addresses some of the material issues related to the epitaxy of Si/SiGe quantum cascade structures, including strain–stress balance and production of strain-relaxed SiGe virtual substrates.

Growth of SiGe-on-insulator and its application as a substrate for epitaxy of strained-Si layer

We report on a simple approach for fabrication of SiGe-on-insulator (SGOI), which contains the growth of Ge on a Si-on-insulator (SOI) substrate and following high-temperature annealing. We discuss the guiding principle for choice of the processing parameters to obtain high-quality SGOI. Furthermore, SGOI was utilized as a substrate for subsequent epitaxial growth of a strained-Si layer. As a result, fluctuation of the strain in the Si film on SGOI was found to be suppressed compared with that on a conventional SiGe virtual substrate, which shows that SGOI grown by our method is promising for the substrate to grow high-mobility strained-Si channel layers.

Quantitative analysis of gate–oxide interface roughening in SiGe/Si virtual substrate-based transistor device structures

Atomic scale roughening of the gate–oxide interface in virtual substrate-based SiGe/Si n-channel metal-oxide-semiconductor field-effect-transistor device structures has been investigated using transmission electron microscopy (TEM). Since the surface of SiGe virtual substrates can be prone to the development of large-scale undulations, the effects of such surface non-planarity on the microstructure of a processed gate–oxide was explored. It was found that the roughness of the interface between the strained Si surface channel and gate–oxide varied significantly (roughness amplitude from 0.2 to 0.6 nm), and correlated with local angular variation of the virtual substrate (VS) surface. These quantitative measurements from electron micrographs were carried out using specially derived computer-based algorithms.