SiGe Virtual Substrates Research Articles

Uniaxial strain relaxation in He+ ion implanted (110) oriented SiGe layers

Uniaxially strained (011)Si is attractive for high performance p-channel metal oxide semiconductor field effect transistor devices due to the predicted high hole mobilities. Here, we demonstrate the realization of purely uniaxially relaxed (011) SiGe virtual substrates by He+ ion implantation and thermal annealing. Perfect uniaxial relaxation is evidenced by precise ion channeling angular yield scan measurements and plan view transmission electron microscopy as predicted theoretically on the basis of the layer symmetry dependent dislocation dynamics. Strikingly, misfit dislocations propagate exclusively along the [01¯1] direction in the (011) oriented crystal and, in contrast to (100)Si, no crosshatch is formed. We describe dislocation formation and propagation inducing strain relaxation of (011)SiGe and enlighten the differences to (100) oriented SiGe on Si.

Investigation of interface characteristics in strained-Si nMOSFETs

We investigate and compare the effects of silicon thicknesses on interface characteristics in strained-Si nMOSFET fabricated on SiGe virtual substrate. Ge out-diffusion effect and slight strain relaxation in Si-cap layer are observed with capacitance–voltage measurements. The low-frequency noise characteristics were used to further investigate the interface transport mechanisms and show the same tendency. Moreover, experimental results show that the unified model, i.e. carrier number fluctuation model, including correlated mobility fluctuation is more suitable to interpret the mechanism of 1/ f noise in strained-Si devices. Carrier number fluctuation dominates the 1/ f noise in weak inversion, but the mobility fluctuation contributes to strong inversion.

DC and 1/ f noise characteristics of strained-Si nMOSFETs using chemical–mechanical-polishing technique

Utilizing chemical–mechanical-polishing (CMP) technique to reduce oxide interface defects and roughness induced from SiGe virtual substrate in strained-Si nMOSFETs has been investigated. Due to the smoother SiO 2/Si interface, an additional 3.5% driving current and 11% transconductance enhancements are found in strained-Si devices with a gate length = 0.5 μm on CMP-treated SiGe virtual substrate, compared to strained-Si devices without CMP process. Moreover, strained-Si devices with CMP process exhibit the lowest 1/ f noise. Under larger gate voltage overdrive, the enhancements become more obvious indicating that the CMP process provides a smoother surface of the strained-Si/SiGe structure.

Fabrication of High Quality SiGe Virtual Substrates by Combining Misfit Strain and Point Defect Techniques

High quality strain-relaxed thin SiGe virtual substrates have been achieved by combining the misfit strain technique and the point defect technique. The point defects were first injected into the coherently strained SiGe layer through the “inserted Si layer” by argon ion implantation. After thermal annealing, an intermediate SiGe layer was grown with a strained Si cap layer. The inserted Si layer in the SiGe film serves as the source of the misfit strain and prevents the threading dislocations from propagating into the next epitaxial layer. A strained-Si/SiGe/inserted-Si/SiGe heterostructure was achieved with a threading dislocation density of 1×10 4 cm −2 and a root mean square surface roughness of 0.87 nm. This combined method can effectively fabricate device-quality SiGe virtual substrates with a low threading dislocation density and a smooth surface.

CMP for High Mobility Strained Si/Ge Channels

AbstractSi/Ge heterostructures are one of the most promising performance boosters for next generation CMOS circuits. Lattice mismatch between Si and Ge enables us to manipulate lattice strain, that is, strain engineering is possible. The strain highly alters band structures and gives rise to band splitting and/or effective mass reduction, which brings significant mobility enhancement of the carriers in the strained channel.High mobility channels such as strained-Si and strained-Ge can be formed on strain-relaxed SiGe buffer layers called SiGe virtual substrates (VS). Since the property of the SiGe VS directly affects that of the overgrown channel layer, creating high-quality SiGe VS is highly required to obtain high performance devices. One critical problem is a very large surface roughness arising on the SiGe VS. So-called crosshatch pattern appears on the surface, irrespective of growth methods. Since strain field coming from the underlying misfit dislocation arrays is responsible for this roughness formation, it is very difficult to create a roughness-free surface.To overcome this problem, we employed chemical mechanical planarization (CMP) for the purpose of eliminating the roughness. Since CMP is established technology for Si wafer production, it is reasonably applicable to SiGe. Adopting the similar process as Si CMP, we demonstrated that an initial roughness of larger than 10 nm was reduced considerably down to less than 1 nm.Post-CMP cleaning is an additional issue of great importance for regrowth of device channel structures. We found that the roughness increased during post-CMP cleaning process due to laterally nonuniform etching rate of the SiGe surface. To overcome this, we optimized the cleaning procedure, especially cleaning solution, and successfully obtained very smooth surface with RMS roughness of less than 0.4 nm, the lowest value ever obtained for SiGe surfaces.The planarized SiGe VS was applied to strained channel structures. Strained Si modulation doped structure was fabricated on the planarized SiGe VS with a Ge concentration of 30 %. The electron Hall mobility obtained from the structure with CMP was 4 times higher than the reference structure without CMP, which is a clear evidence that the roughness-related carrier scattering can be well suppressed by the planarization. Strained Ge channel modulation doped structure was also fabricated on the SiGe VS with much higher Ge concentration (65 %). Although the roughness was much larger than 10 nm due to the high Ge concentration, the surface smoothness less than 1 nm was obtained by CMP. As a result, hole mobility enhancement factor over the reference sample without CMP was found to reach as high as 8 at low temperature and 1.8 at room temperature. These results clearly indicate that CMP is very promising technology for high performance strained Si/Ge based CMOS circuit.

Growth and structural properties of SiGe virtual substrates on Si(1 0 0), (1 1 0) and (1 1 1)

The growth kinetics and structural properties of nominally 15–45% SiGe virtual substrates (VS) on Si(1 0 0), Si(1 1 0) or Si(1 1 1) substrates have been investigated. Our “best” (1 0 0) growth procedure has been used, which leads to the formation of high-quality SiGe(1 0 0) VS with threading dislocation densities around 10 5 cm −2. The mean SiGe growth rate (GR) on (1 0 0) is higher than the one on (1 1 1), which is itself higher than the one on (1 1 0) (more precisely: GR(1 1 0) ∼0.6×GR(1 0 0) and GR(1 1 1) ∼0.85×GR(1 0 0)). The trend is the opposite one for the mean Ge content, with %Ge×1.5 and ×1.2 higher on (1 1 0) and (1 1 1) than on (1 0 0), respectively. The Ge concentration dependence on mass-flow ratio has been quantified using a x Ge/(1− x Ge)= p(F(GeH 4)/F(SiH 2Cl 2)) relationship for all surface orientations. We have obtained (1 1 0) and (1 1 1) p values 1.8–2.0 and 1.3–1.5 times higher than on (1 0 0). We have otherwise studied the structural properties of SiGe(1 0 0), (1 1 0) and (1 1 1) VS. Original surface morphologies have been evidenced for each surface orientation. Cross-hatch, “half cross-hatch” and triangular arrays have been observed on (1 0 0), (1 1 0) and (1 1 1), with respectively slight and strong surface roughening for the latter two orientations. Higher defect densities have been evidenced by TEM on SiGe(1 1 0) and (1 1 1) VS than on (1 0 0). Whereas stacking faults have propagated from the Si(1 1 1) substrate all the way up to the surface, these defects are mostly confined in the SiGe ramp when growing on (1 1 0), with a 0.5 μm defect-free area on top. Threading dislocation densities (from Schimmel defect etching) are roughly equal to 10 8 cm −2 on both Si 0.72Ge 0.28 (1 1 0) and Si 0.80Ge 0.20 (1 1 1) VS. Finally, SiGe VS are crystalline whatever the Si surface orientation as shown by the coherent X-ray diffraction profiles or reciprocal space maps obtained. SiGe(1 0 0) and (1 1 0) VS are both fully relaxed, whereas the (1 1 1) ones may be in a tensily strained configuration.

Reverse graded relaxed buffers for high Ge content SiGe virtual substrates

An innovative approach is proposed for epitaxial growth of high Ge content, relaxed Si1−xGex buffer layers on a Si(001) substrate. The advantages of the technique are demonstrated by growing such structures via chemical vapor deposition and their characterization. Relaxed Ge is first grown on the substrate followed by the reverse grading approach to reach a final buffer composition of 0.78. The optimized buffer structure is only 2.8μm thick and demonstrates a low surface threading dislocation density of 4×106cm−2, with a surface roughness of 2.6nm. The buffers demonstrate a relaxation of up to 107%.

Strain in Epitaxial Si/SiGe Graded Buffer Structures Grown on Si (100), Si (110) and Si(111): a Raman Spectroscopy Study

We report preliminary results on the Raman characterization of strained-Si films pseudomorphically grown on (001), (110) and (111) SiGe virtual substrates. Because the relation between strain or stress and the Raman frequencies are complex, we first derive the strain-shift coefficients for the different substrate orientations considered in this work. Then, visible and near-UV Raman spectroscopies were used to extract the in-plane lattice parameter of the virtual substrate and the strain in the thin silicon epitaxial layers grown on top. Finally, we investigated the in-plane strain distribution in strained Si/SiGe buffer layers grown on (110) and (111) silicon substrates by Raman imaging. In-plane strain fluctuations are observed both in the epilayer and the virtual substrate for all substrate orientations.

Noise Properties of High-Mobility, 80 nm Gate Length MOSFETs on Supercritical Virtual Substrates

It was found that for strained Si channel layers of supercritical thickness on relaxed SiGe virtual substrates, the 1/f noise on average is maintained at the same level as in unstrained devices. Short gate length nMOSFETs were analyzed statistically and the noise level variation, across a large number of samples, was similar in strained and unstrained devices. The obtained noise level variation was partly related to gate length fluctuations across the wafer, which was evident from a small VT fluctuation.

Structural and electrical characterisation of ion-implanted strained silicon

The production of low resistance ultra-shallow junctions for e.g. source/drain extensions using low energy ion-implantation will be required for future CMOS devices [H. Wakabayashi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, K. Yoshida, K. Takeuchi, Y. Ochiai, T. Mogami, T. Kunio, Trans. Electron Devices 49 (2002) 89–94]. This architecture will require implants which demonstrate high electrical activation and nm range depth profiles. We investigate the properties of Sb implants in tensile strained silicon due to their potential to satisfy these criteria and the mobility enhancements associated with tensile strained silicon. Low energy (in this case 2 keV) implants coupled with Sb’s large atomic radius are capable of providing ∼10 nm implant depths. In addition to this, Sb demonstrates higher electrical activation in the presence of tensile strain, when compared with the more traditional n-type dopant As [N.S. Bennett, N.E.B. Cowern, A.J. Smith, R.M. Gwilliam, B.J. Sealy, L. O’Reilly, P.J. McNally, G. Cooke, H. Kheyrandish, Appl. Phys. Lett. 89 (2006) 182122]. We now report on the initial results of an ongoing systematic study over a wide silicon tensile strain range (from 0.4% to 1.25% strain) in order to establish clear strain-related trends. Graded Si 1− x Ge x virtual substrates (VS) with 0.1 ≤ x ≤ 0.3 were used as template substrates upon which tensile Si layers were grown. Prior to implantation the quality of the strained layer and SiGe buffer is assessed using UV micro-Raman spectroscopy (μRS), synchrotron X-ray topography (SXRT) and high-resolution X-ray diffraction (HR-XRD). For measurements of strain following implantation, HR-XRD is found to be more useful than μRS because of additional carrier-concentration induced Si Raman peak shifts. These shifts obscure small changes in the strain state, and are a result of the degenerate doping levels achieved in these samples (∼7 × 10 20 cm −3). Using X-ray techniques, at Ge concentrations >23% (i.e. ɛ > 0.9%) we find clear evidence of tilt in the SiGe VS, which impacts on the quality of the strained Si. Additionally, stacking faults have been detected non-destructively in the higher strain samples ( ɛ = 1.25%, VS = Si 0.7Ge 0.3) using SXRT in transmission mode.

Low-frequency noise of strained-Si nMOSFETs fabricated on a chemical–mechanical-polished SiGe virtual substrate

The low-frequency noise characteristics in strained-Si nMOSFETs, utilizing the chemical–mechanical-polishing (CMP) treated SiGe virtual substrate have been investigated and compared with the results obtained on strained-Si counterparts without CMP technology. Additional 10.6% mobility improvement and four times lower 1/f noise over 1–100 Hz was obtained for strained-Si devices with the CMP process, indicting that the CMP process provides a smoother surface for the strained-Si/SiGe structure. Moreover, experimental results show that carrier number fluctuation, and not the unified model, is more suitable to interpret the mechanism of 1/f noise in strained-Si devices with the CMP process.

Strain engineered Si∕SiGe resonant interband tunneling diodes with outside barriers grown on Si0.8Ge0.2 virtual substrates

Si-based resonant interband tunneling diodes (RITDs) grown on commercially available Si0.8Ge0.2 virtual substrates were studied. Peak-to-valley current ratios (PVCRs) were improved by utilizing strain induced band offsets to 3.5 with a peak current density (Jp) of 161A∕cm2. More specifically, a tensilely strained Si layer on the p-side and a compressively strained Si0.5Ge0.5 layer on the n-side were added to the design to form enhanced potential barriers away from the tunneling junction. The outside barriers deepen the respective hole and electron quantum wells and also block nonresonant tunneling current, which improved the PVCR significantly. However, due to the large surface roughness of the SiGe virtual substrates used in this study, the RITDs grown on Si0.8Ge0.2 substrates exhibit a smaller PVCR overall than RITDs optimized on standard Si substrates. Better performance is expected by using higher quality SiGe substrates with smaller surface roughness.

Reduced Pressure–Chemical Vapour Deposition of Si/SiGe heterostructures for nanoelectronics

We have first of all quantified the impact of pressure on Si and SiGe growth kinetics. Definite growth rate and Ge concentration increases with the pressure have been evidenced at low temperatures (650–750 °C). By contrast, the high temperature (950–1050 °C) Si growth rate either increases or decreases with pressure (gaseous precursor depending). We have then described the selective epitaxial growth process we use to form Si or Si 0.7Ge 0.3:B raised sources and drains on ultra-thin patterned Silicon-On-Insulator (SOI) substrates. We have afterwards presented the specifics of SiGe virtual substrates and of the tensile-strained Si layers grown on top (used as templates for the elaboration of tensily strained-SOI wafers). The tensile strain, which can be tailored from 1.3 up to 3 GPa, leads to an electron mobility gain by a factor of 2 in n-Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) built on top. High Ge content SiGe virtual substrates can also be used for the elaboration of compressively strained Ge channels, with impressive hole mobility gains (×9) compared to bulk Si. After that, we have described the main structural features of thick Ge layers grown directly on Si (that can be used as donor wafers for the elaboration of GeOI wafers or as the active medium of near infrared photo-detectors). Finally, we have shown how Si/SiGe multilayers can be used for the formation of high performance 3D devices such as multi-bridge channel or nano-beam gate-all-around FETs, the SiGe sacrificial layers being removed thanks to plasma dry etching, wet etching or in situ gaseous HCl etching.

Strained-Si nMOSFET formed on very thin SiGe buffer layer fabricated by ion implantation technique

We fabricated strained-Si n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) on very thin SiGe buffer layers. The ion implantation technique was successfully employed and the Si 0.83Ge 0.17 relaxed layer with the thickness as small as 100 nm was obtained. As a result, 2.0 times drive current, 2.6 times transconductance and 1.6 times mobility enhancements over the control Si device were obtained, indicating that the ion implantation technique is very promising for realization of high performance strained-Si devices on very thin SiGe virtual substrates.

Observation of in-plane strain fluctuation in relaxed SiGe virtual substrate

We investigate the morphology and strain distribution of the surface crosshatch undulation on a strain-relaxed SiGe layer grown on a low-temperature Si buffer layer by atomic force microscopy and spatially-resolved UV-Raman spectroscopy. Surface crosshatch undulation resulted from misfit dislocations at the SiGe/Si interface is associated with the strain relaxation in the SiGe layer. By means of thermal annealing, strain relaxes and the inhomogeneous in-plane strain fluctuation can be eliminated.

Nanometer strain profiling through Si/SiGe quantum layers

For the first time, nanometer-scale strain resolution is demonstrated using conventional Raman spectroscopy to profile strain through thin epitaxial Si/SiGe layers used as high mobility metal oxide field effect transistor channels. The strained layers were grown using ultrahigh vacuum chemical vapor deposition on relaxed SiGe virtual substrates. We observe how strain varies through the layer with 1.2 nm depth resolution. This is achieved by shallow angle (0.7°) bevelling. Tensile strain is found to be maximum at the buried Si/SiGe interface and decreases toward the surface. The partial surface strain relaxation is considered to be due to the imminence of the critical thickness. The bevel process has been characterized and does not impact results. SiGe composition and strained layer thickness are also determined and are in excellent agreement with secondary ion mass spectroscopy and x-ray diffraction data. The technique is proven to have 1 nm resolution in thickness measurements. Strain throughout the epitaxial layer stack has also been investigated. We show that the undulating surface morphology characteristic of relaxed SiGe alloys generated using compositional grading relates to periodic fluctuations in the strain fields in the SiGe virtual substrate, which are transferred to the overlying tensile strained Si. The resulting peak-peak variation in the tensile strained Si is determined to be 0.1%.

Advanced semiconductor diagnosis by multidimensional electron‐beam‐induced current technique

We present advanced semiconductor diagnosis by using electron-beam-induced current (EBIC) technique. By varying the parameters such as temperature, accelerating voltage (V(acc)), bias voltage, and stressing time, it is possible to extend EBIC application from conventional defect characterization to advanced device diagnosis. As an electron beam can excite a certain volume even beneath the surface passive layer, EBIC can be effectively employed to diagnose complicated devices with hybrid structure. Three topics were selected to demonstrate EBIC applications. First, the recombination activities of grain boundaries and their interaction with Fe impurity in photovoltaic multicrystalline Si (mc-Si) are clarified by temperature-dependent EBIC. Second, the detection of dislocations between strained-Si and SiGe virtual substrate are shown to overcome the limitation of depletion region. Third, the observation of leakage sites in high-k gate dielectric is demonstrated for the characterization of advanced hybrid device structures.

Influence of the Ge concentration in the virtual substrate on the low frequency noise in strained-Si surface n-channel metal-oxide-semiconductor field-effect transistors

We report on low frequency noise and field-effect mobility in strained-Si surface n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) grown on relaxed virtual substrates with a Ge concentration varying between 0% and 30%. An increased Ge concentration results in higher intrinsic field-effect mobility, increasing from 380cm2V−1s−1 for the unstrained channel to 865cm2V−1s−1 for the strained-Si MOSFET on 30% relaxed SiGe virtual substrate. However, the higher mobility is traded off for increased substrate leakage currents and increased 1∕f (flicker) noise. It is suggested that flicker noise is due to traps in the oxide layer. The density of traps increases from 2×1017eV−1cm−3 for 0% Ge to 2.3×1018eV−1cm−3 for the 30% Ge virtual substrate.

On the electron mobility enhancement in biaxially strained Si MOSFETs

This paper reports a detailed experimental and simulation study of the electron mobility enhancement induced by the biaxial strain in (0 0 1) silicon MOSFETs. To this purpose, ad hoc test structures have been fabricated on strained Si films grown on different SiGe virtual substrates and the effective mobility of the electrons has been extracted. To interpret the experimental results, we performed simulations using numerical solutions of Schroedinger–Poisson equations to calculate the charge and the momentum relaxation time approximation to calculate the mobility. The mobility enhancement with respect to the unstrained Si device has been analyzed as a function of the Ge content of SiGe substrates and of the operation temperature.

Characterization of biaxial stressed silicon by spectroscopic ellipsometry and synchrotron x-ray scattering

Spectroscopic ellipsometry (SE) and synchrotron x-ray scattering have been applied to the non-destructive characterization of strained silicon (ε-Si). SE data from 250 nm to 500 nm were acquired from three epitaxial ε-Si samples grown on silicon germanium (SiGe) virtual substrates by chemical vapor deposition. Additional structural and compositional data were collected using x-ray scattering. The SE data were fitted by a two-step procedure involving the use of a parametric dielectric function model that is especially suitable for crystalline semiconductors. By monitoring the shift of the E1 critical point in the fitted dielectric function spectrum, the tensile strain of ε-Si can be determined from the known elastic constants and deformation potentials of Si. Strain values obtained are generally in agreement with the UV Raman measurements. The structural characteristic of the sample with the highest germanium concentration in the virtual substrate was further studied by reciprocal space mapping and atomic force microscopy.