Reduced Pressure–Chemical Vapour Deposition of Si/SiGe heterostructures for nanoelectronics

Abstract

We have first of all quantified the impact of pressure on Si and SiGe growth kinetics. Definite growth rate and Ge concentration increases with the pressure have been evidenced at low temperatures (650–750 °C). By contrast, the high temperature (950–1050 °C) Si growth rate either increases or decreases with pressure (gaseous precursor depending). We have then described the selective epitaxial growth process we use to form Si or Si 0.7Ge 0.3:B raised sources and drains on ultra-thin patterned Silicon-On-Insulator (SOI) substrates. We have afterwards presented the specifics of SiGe virtual substrates and of the tensile-strained Si layers grown on top (used as templates for the elaboration of tensily strained-SOI wafers). The tensile strain, which can be tailored from 1.3 up to 3 GPa, leads to an electron mobility gain by a factor of 2 in n-Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) built on top. High Ge content SiGe virtual substrates can also be used for the elaboration of compressively strained Ge channels, with impressive hole mobility gains (×9) compared to bulk Si. After that, we have described the main structural features of thick Ge layers grown directly on Si (that can be used as donor wafers for the elaboration of GeOI wafers or as the active medium of near infrared photo-detectors). Finally, we have shown how Si/SiGe multilayers can be used for the formation of high performance 3D devices such as multi-bridge channel or nano-beam gate-all-around FETs, the SiGe sacrificial layers being removed thanks to plasma dry etching, wet etching or in situ gaseous HCl etching.