Facet-Free Si Selective Epitaxial Growth Adaptable to Elevated Source/Drain MOSFETs with Narrow Shallow Trench Isolation

Abstract

A novel selective epitaxial growth (SEG) process that realizes a facet-free elevated source/drain (S/D) is proposed. The key points are the appropriate selection of the gate-sidewall material and its structural improvement. It was observed that the facet was not formed adjacent to SiN in contrast to the SiO2 case. Therefore, SiN is selected as a gate-sidewall. The novel gate-sidewall is constructed from a SiN sidewall and SiO2 liner layer which acts as a sidewall reactive ion etching (RIE) stopper. The SiO2 liner layer is lateral etched by wet treatment. By the SEG process, the facet, which is formed adjacent to the SiO2 liner is screened out within the lateral etched region, and no facet is observed along the SiN sidewall. Si lateral overgrowth on the shallow trench isolation (STI) region was also confirmed to be controllable in the facet-free SEG process. This novel SEG process was found to be successfully adapted to facet-free elevated S/D.