SiGe Channel Research Articles

Threshold voltage model for quantum-well channelpMOSFET with poly SiGe gate

In this paper, threshold voltage model of quantum-well channel pMOSFET with p+polycrystalline SiGe gate and its cut-in voltage model were established based on solving Poisson equation while considering the impact of free carrier. The effects of relevant parameters (Ge concentration of poly SiGe gate, Ge concentration of quantum-well SiGe channel, thickness of oxide layer, thickness of Si cap layer, doping content of quantum-well SiGe channel, and doping content of substrate) on threshold voltage and cut-in voltage of the parasitic channel was analysed by numerical analysis, and obtained the methods to restrain the opening of parasitic channel. The results of the models are in good agreement wih that of experiment reported as well as of ISE simulation.

The Effect of a Si Capping Layer on RF Characteristics of High-$k$/Metal Gate SiGe Channel pMOSFETs

We present a comparative study of the effects of a Si capping layer on SiGe channel pMOSFETs used for radio-frequency (RF) applications. In Si-capped devices, the drive current increases because Si/SiGe heterojunction layers form a SiGe quantum well, which reduces carrier scattering. Conversely, SiGe samples without a Si capping layer suffer severe interface degradation, due to Ge diffusing into the gate dielectric. Devices using a Si capping layer have enhanced RF performance and reduced low-frequency noise, which is a key factor affecting phase noise. There is an increase in the RF figures of merit. These benefits indicate that a Si capping layer should be used in SiGe channel pMOSFETs.

New opportunities for SiGe and Ge channel p-FETs

A thin body (fully depleted) strained SGOI device structure (FDSGOI), and a strained SiGe channel layer on SOI, were fabricated using scaled high- κ gate dielectrics and metal gate technology. The uniaxial strain effect and corresponding drive current enhancement reported by Irisawa et al. [1] for narrow-width devices was investigated on these structures. Although the strained FDSGOI device structure exhibited reduced off-state leakage compared to thicker body devices, and long-channel drive current enhancement under uniaxial strain, the loss of drive current enhancement at short channel length led to uncompetitive I ON– I OFF characteristics. The SiGe on SOI structure showed the highest long-channel drive current enhancement (nearly 3×) in the narrowest devices, and also showed a significant reduction in off-state current. This trend was maintained down to the shortest channel lengths studied here and resulted in I ON– I OFF characteristics that were competitive with contemporary uniaxial strained Si channel devices.

Electrical characteristics of SiGe channel MOS devices with high-k/metal gate incorporated with nitrogen by plasma immersion ion implantation

High-k gated metal–oxide–semiconductor devices with SiGe channel and nitridation treatment using plasma immersion ion implantation (PIII) were studied in this work. After metal gate deposited, PIII nitridation treatment was performed at an energy of 2.5 keV for 10 min. Experimental results show that the electrical characteristics of high-k dielectric can be obviously improved by PIII nitridation. For instance, the values of stress-induced leakage are reduced more than 50% and the value of stress-induced flat-band voltage shifts are reduced more than 33%. The equivalent oxide thickness (EOT) value of MOS device with 30% Ge content in SiGe channel and PIII nitridation can be reduced to 9.6 Å.

Improvement on programming and erasing speeds for charge-trapping flash memory device with SiGe buried channel

SiGe buried channel with different Ge contents and various thicknesses of Si-cap layer on operating characteristics of charge-trapping (CT) flash devices were studied in this work. The results show that the programming and erasing speeds of CT flash devices are significantly improved by employing SiGe buried channel. Enhancement up to merely 20 times on programming speed was achieved. The retention characteristics of flash devices are satisfactory with suitable Ge content in SiGe buried channel and thickness of Si-cap layer. From the measurement of secondary ion mass spectroscopy, the operation characteristics of flash devices with SiGe channel were sensitive to the distribution of Ge atoms.

High Mobility SiGe Channel NonPlanar Devices

We report on the promise of using SiGe channel FinFETs for high performance CMOS for the sub-22nm node. Devices with Si, stacked SiGe/Si, shell/core SiGe/Si and homogeneous SiGe fins with (110) and (100) surface orientations were fabricated and characterized. The stacked SiGe/Si fin device exhibited a dual turn-on due to the SiGe and Si regions. The shell/core SiGe/Si fin device mobility was 30% greater than the Si fin. The homogeneous SiGe fin device with a (110) orientation had a mobility 3.6X higher than the Si fin device with a (100) orientation.

Investigation of Novel Si/SiGe Heterostructures and Gate Induced Source Tunneling for Improvement of p-Channel Tunnel Field-Effect Transistors

This paper presents optimization techniques for 20 nm channel length novel Si/SiGe heterojunction p–i–n p-channel tunnel field-effect transistors using extensive device simulations. Three different device architectures are compared. It is shown that depending on the Ge mole fraction in SiGe and the gate voltage, the tunneling could be from the channel to source or within the source only. Due to this, a very careful optimization of the Ge mole fraction is required to achieve optimum performance. It is also shown for the first time that a vertical gate induced source tunneling is present in the devices and that this could be utilized for improving ON state current by increasing the gate–source overlap. Of the three device architectures compared, the structure with SiGe channel and Si source/drain is found to give better ON state current. Gate length scalability is found to be superior for the structure with SiGe source, and Si channel/drain.

Residual order in the thermal oxide of a fully strained SiGe alloy on Si

Introduction Oxidation of SiGe alloy has been a target of research for both fundamental and technological reasons, as in the case of Si oxidation. It has been expected as the fabrication process for the gate oxide of SiGe channel metal oxide semiconductor field effect transistors (MOSFETs), which allows higher carrier mobility than that of Si channel MOSFETs [1]. In recent years, it has also been employed in the fabrication of SiGe-oninsulator and Ge-on-insulator substrates [2]. These substrates are employed to realize high-speed MOSFETs with channel materials of strained Si, SiGe, and Ge. However, the oxidation mechanism of SiGe alloy is still open to question, due to the complexity caused by lattice strain and diffusion of Ge atoms. The most characteristic phenomenon of SiGe oxidation is that Ge atoms are ejected from the interface between the surface oxide and the SiGe layer without the incorporation of Ge atoms into the oxide layer. Ge atoms accumulate at the SiO2/SiGe interface and diffuse into the SiGe layer [1,2]. In the case of a strained SiGe layer epitaxially grown on a Si substrate, the effects of strain relaxation and defect generation during the oxidation process must be taken into account. It is important to investigate the atomic structure of the thermally oxidized layer, because it allows us to understand what really happens at the oxidized interface. In the case of the thermally oxidized layer of Si, the Si atoms in the oxide layer still maintain order, which originates from the diamond structure of the parent Si crystal, although the structure appears to be amorphous at a glance. This provides an actual picture of the oxidation process and explains the almost perfect properties obtained by electric measurements of the SiO2/Si interface. In this study, the residual order in the thermal oxide layer on a fully strained SiGe alloy was investigated.

SiGe SEG Growth for Buried Channels p-MOS Devices

Different selective epitaxial growth processes to deposit buried SiGe channels with Ge contents in the range of 25-55% and with an ultra thin Si capping layer have been successfully developed and implemented in pMOS device flows. Relatively low deposition temperatures assure the absence of SiGe islands and enable high quality strained SiGe layers. The required low growth temperature governed the choice of precursors used. In this contribution we review in detail the developed SiGe processes together with the deposition of the ultra thin Si cap layer. Electrical data obtained on the devices with incorporated Si0.75Ge0.25 and Si0.55Ge0.45 buried channels are presented as well.

A CLOSED-CYCLE REFRIGERATOR BASED PULSED MAGNET SYSTEM

A low cost 12 T pulsed magnet system has been integrated with a closed-cycle helium refrigerator. The copper solenoid is directly immersed in liquid nitrogen for reduced electrical resistance and more efficient heat transfer. This ensures a minimal delay of few minutes between pulses. The sample is mounted on the cold finger of the refrigerator and, along with the surrounding vacuum shroud, is inserted into the bore of the solenoid. When combined with software lock-in signal processing to reduce noise, quick but accurate measurements can be performed at temperatures 4 K-300 K up to 12 T. Quantum Hall effect data in a p -channel SiGe / Si heterostructure has been used to calibrate the instrument against a commercial superconducting magnet. Its versatility as a routine characterization tool is demonstrated by measuring parallel conduction in Si / SiGe modulation doped heterostructures.

Effects of Ge content in SiGe channel on electrical characteristics of high-k gated MOS device

Metal-oxide-semiconductor capacitors with HfAlO high-k gate dielectric deposited by Atomic Layer Deposition (ALD) and SiGe channel were studied in this work. A thin Si layer was also grown upon SiGe channel layer as a capping layer to form a Si/SiGe/Si structure on substrate. Different Ge contents from 7% to 32% in SiGe channel on electrical characteristics of MOS device were investigated. Based on gate leakage and reliability properties of MOS devices, the optimal Ge content in SiGe channel to achieve enough mobility enhancement is around 20%. The improvement of electrical characteristics includes low leakage current, small EOT value and good reliability.

Opportunities and Challenges for Germanium and Silicon-Germanium Channel p-FETs

The electrical behavior of SiGe and pure Ge channel p-FET devices will be presented and discussed in this paper. By fabricating short channel SiGe, relaxed Ge and strained Ge channel devices with scaled high-κ/metal gate stacks, we demonstrate three main advantages of using these types of devices: i) more aggressive TINV scaling of the gate dielectric due to lower temperature processing, ii) band gap engineering to allow better control of threshold voltage and possibly iii) lower external resistance due to the higher B activation in these materials. The main drawback inherent to relaxed Ge and biaxially strained Ge and SiGe channels is that the ability to have improved transport properties without the need for external stressors always seems to come with a large penalty in off state leakage. The ION and IOFF in these devices are compared to recent work by others and a general trend is observed.

The Challenges in Introducing PMOS Dual Channel in CMOS Processing

The benefit of a SiGe channel in the adjustment of the threshold voltage in PMOS devices is outlined. However, difficulties in the implementation make the full CMOS integration challenging. We examine these difficulties of implementation and the complexities of the processes. The issues are divided into two categories to better understand the complexity: active area related and complementary process related. In particular, the process issues associated with epitaxy, gate etch, silicide and lithography are particularly examined. It is concluded that the issues can be overcome with excellent transistor results.

A study on aggressive proximity of embedded SiGe with comprehensive source drain extension engineering for 32 nm node high-performance pMOSFET technology

In general, closer proximity of embedded SiGe (eSiGe) source drain (S/D) structure to the channel improves p-channel metal oxide semiconductor field-effect transistor (pMOSFET) performance because of the higher stress in the channel. However, we found the critical optimization methodology which has a relation between boron diffusion modulation in SiGe and short channel effect (SCE) in the context of the eSiGe proximity change. Therefore, additional source drain extension (SDE) optimization is required to improve device performance with closer eSiGe proximity focusing on the parasitic resistance reduction. As a result of the optimization, we have demonstrated high drive current of 755 μA/μm at V dd = 1.0 V, I OFF = 100 nA/μm, 30 nm gate length pMOSFET.

Impact of Ge Content on Flicker Noise Behavior of Strained-SiGe p-Type Metal–Oxide–Semiconductor Field-Effect Transistors

The DC characteristic and low-frequency (1/ f) noise behavior of strained-Si1-xGex p-type metal–oxide–semiconductor field-effect transistors (pMOSFETs) with 15 and 30% Ge channel have been investigated and compared with those of Si control counterparts. Enhancement in effective hole mobility of 24 and 45% were obtained in strained-SiGe devices with a 15 and 30% Ge channel, respectively. The strained-SiGe pMOSFETs with a higher Ge buried channel exhibit lower 1/ f noise, indicating that more carriers are confined in the SiGe channel and interface scattering is remote. Moreover, we also found that the Ge concentration plays an important role in the noise mechanism. A new observation shows that carrier number fluctuation is more suitable for interpreting the mechanism of 1/ f noise in strained-SiGe devices with 30% Ge channel, while both number fluctuation noise and mobility fluctuation noise are likely to contribute to the characteristics of SiGe pMOSFETs with 15% Ge and the Si control device.

High Mobility SiGe p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Epitaxially Grown on Si(100) Substrates with HfSiO2 High-k Dielectric and Metal Gate

High mobility metal–oxide–semiconductor field-effect transistors (MOSFETs) are demonstrated on strained or relaxed SiGe-on-Si heterostructures with Si cap/SiGe channel quantum well structures. Si cap processing is frequently used to enhance hole mobility of SiGe pMOSFETs by improving the interface quality of high-k gate dielectrics and SiGe channels. However, one of mechanisms that limits future gate oxide scaling is Ge enhanced Si oxidation, which results in a thick Si oxide interface layer. In this work, without using Si cap process, we have fabricated high mobility SiGe channel pMOSFETs after optimizing epitaxial SiGe-on-Si and high-k dielectric/metal gate process. High mobility with low off-state current have been achieved and correlated with epitaxial SiGe-on-Si processes.

The progress and challenges of threshold voltage control of high- k/metal-gated devices for advanced technologies (Invited Paper)

This paper discusses recent progress in and challenges of threshold voltage control for advanced high- k/metal-gated (HKMG) devices. It presents the impact on threshold voltage ( V t) control of incorporating La and Al into HKMG devices. A dipole moment model explaining V t tuning of HfSiON/metal-gated MOSFETs is proposed. In addition, a dual channel scheme that allows La 2O 3 capping in NMOS and a SiGe channel in PMOS to achieve acceptable V t for HKMG CMOS devices will be discussed. Also shown is the impact of the robustness of the SiO 2/Si interface on the HKMG MOSFET V t-equivalent oxide thickness (EOT) roll-off. Finally, techniques to improve the interface quality of a HKMG stack will be discussed.

Investigation of Power MOSFET with Strained SiGe Channel

Two trench-gated power MOSFETs using strained SiGe channel are proposed to further reduce specific on-state resistance. The first is a multiple SiGe and Si layer structure for N-channel MOSFET. A 30nm Si0.85Ge0.15 layer and a 50nm Silicon layer are grown by RPCVD alternatively to achieve sufficient channel length which is longer than critical thickness before the trench etches. The second method is to form the strained SiGe layer along the trench sidewall for P-channel MOSFET. A single Si0.85Ge0.15 layer of 30nm thick is grown after the trench etches. It is expected that the channel mobility in the vertical direction will be increased by up to 40% and 60% for electrons and holes respectively compared to conventional silicon device with same structure and doping profile. The on-state resistance is predicted to be reduced by 12% and 20% for N-channel and P-channel MOSFET accordingly.

Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High- $k$/Metal Gate Stacks Directly on SiGe

This letter addresses mechanisms responsible for a high gate leakage current (Jg) and a thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with sub-1-nm equivalent-oxide-thickness (EOT) high-k /metal gate stack. The primary mechanism limiting EOT scaling is Ge-enhanced Si oxidation resulting in a thick (1.4-nm) SiOx interface layer. A secondary mechanism, i.e., Ge diffusion (ges3%) into high- k, results in high Jg. In the framework of this understanding, we optimized a high-k nitridation process to form as an efficient diffusion barrier, which reduces both O and Ge diffusion resulting in the total gate stack EOT ~ 0.9 nm with J g comparable to that of bulk Si substrate samples. The proposed plasma nitridation process enables fabrication of the sub-1-nm EOT gate-first gate stack with HfSiON dielectric directly on SiGe without Si cap.

SiGe channels for higher mobility CMOS devices

AbstractSilicon germanium (SiGe) is considered to substitute silicon (Si) as channel material of p-type MOSFET in future CMOS generations due to its higher hole mobility. In this work we investigate SiGe channels with a germanium concentration of 23 at% and 30 at%, even though the mobility is expected to be higher with even more germanium in the alloy. Low pressure chemical vapor deposition was used for SiGe deposition. A state of the art CMOS process including high-k dielectric and metal gate electrode was applied for fabrication of sub 50 nm gate length devices. As expected from the SiGe channel conduction and valence band offset the threshold voltage of the devices is influenced. The gate stack was directly deposited onto the SiGe layer consisting of a chemically grown base oxide, hafnium-based dielectric and titanium nitride gate electrode. C-V and I-V measurements show comparable CET and leakage values for the high-k metal gate stack on Si and SiGe channels. The trap density at the channel dielectric interface was determined using the charge pumping technique. The device characteristics of n- and p-MOSFETs with SiGe channels are compared to conventional Si channel devices. Short channel mobility was extracted with the gM,LIN-Method.