SiGe Channel Research Articles

Scaling the SiGe channel pmetal–oxide–semiconductor field effect transistor: The case for p+SiGe gates

A theoretical study of the scalability of the SiGe channel pmetal–oxide–semiconductor field effect transistor to the 0.1 μm generation is presented. Devices with n+ polysilicon gates, p+ polysilicon gates, and intermediate workfunction p+ SiGe gates were considered. It was found that short channel effects became severe in the n+ gated device for channel lengths below 0.15 μm. The p+ gated device provided excellent short channel behavior, but suffered from a very poor crossover voltage. The best compromise between short channel effects and crossover voltage was obtained with the p+ SiGe gate, which gave −VCROSS close to VDD and VDIBL≈98 mV in the 0.1 μm generation.

Radiation-induced back-channel leakage in SiGe CMOS on silicon-on-sapphire (SOS) technology

We report the first results of a high-energy gamma irradiation experiment on SiGe CMOS on silicon-on-sapphire (SOS) technology. In contrast to bulk Si CMOS, with increasing total dose the pFETs develop a significant off-state leakage, while the nFETs show a reduction in the leakage, which we attribute to negative charge trapping at the back Si-sapphire interface. Both the Si and SiGe pFETs showed the enhancement in leakage, suggesting that the leakage mechanism was not related to the SiGe channel. When the devices were cooled to liquid-nitrogen temperature, the leakage disappears completely, suggesting that the trapping mechanism is strongly temperature dependent.

SiGe nMOSFETs with gate oxide grown by low temperature plasma anodisation

The characterisation of strained surface channel SiGe nMOSFETs with gate oxide grown by low temperature plasma anodisation is described. We report excellent off-state leakage currents and zero field mobilities of 640 and 420cm 2/Vs for Si and SiGe devices respectively. Reduction in SiGe mobility is primarily attributed to increased interface state scattering in the absence of any increased surface roughness as observed in high resolution microscopy. The oxide composition is mixed and conservation of crystallinity of SiGe during oxidation is observed via RBS analysis.

DC and low-frequency noise characteristics of SiGe p-channel FETs designed for 0.13-μm technology

The impact of hole confinement on the DC and low frequency noise in SiGe p-channel FETs is investigated by comparison with Si p-FETs produced by the same technology. The relative spectral power density of low frequency (1/f) noise in SiGe pFETs is found to be significantly lower than in Si devices. This is mainly attributed to the physical separation of the holes confined in the SiGe channel from the Si/SiO/sub 2/ interface. The low value of SiGe channel noise proves the good quality of epilayers and heterointerfaces, as also revealed by the TEM cross section.

Hole confinement and low-frequency noise in SiGe pFETs on silicon-on-sapphire

We present the dc, ac, and low-frequency noise characteristics of SiGe channel pFETs on silicon-on-sapphire (SOS). The SiGe pFETs show higher mobility, transconductance, and cutoff frequency compared to the Si control devices. A significant reduction in low-frequency (1/f) noise is observed in the SiGe pFETs, and understood to be the result of a lower border trap density sampled at the Fermi-level due to the valence band offset. The linear g/sub m/ of the SiGe pFET's at 85 K shows a secondary peak which is attributed to the turn-on of the surface channel.

State of Stress and Critical Thickness of Strained Small-Area SiGe Layers

We present an approach in equilibrium theory for strain relief in small-area heteroepitaxial SiGe/Si structures, which includes surface and film-edge induced relaxation effects. With a view to computer simulation, the state of stress and shear components on the slip planes of strained mesa-like SiGe/Si systems are treated here in a simple analytical form in terms of strain and stress components, valid in linear elasticity. The two-dimensional analysis yields a complete description of the state of plane stress of small-area structural elements in a consistent manner. The present system of equations is generally sufficient to quantitatively determine the lowered stress components of stable, metastable, and plastically deformed finite strained layers. It is shown that there is a significant decrease in heteroepitaxial film stress as a function of material and size characteristics of the SiGe/Si system that allows one to increase substantially the critical layer thickness for loss of coherency for a given Ge content. The equilibrium theory proposed here provides guidance for computer simulation to configure stable small-area SiGe deposits for the development of technologies in which stress problems must be alleviated. A complete input deck for stress simulation including a run is given. The developed physics and computer simulation can be used for the design of small-geometry heterojunction bipolar transistors and SiGe channel MOSFETs, and for estimation of stress-related problems in sub-micron size devices.

Characterization and profile optimization of SiGe pFETs on silicon-on-sapphire

We present the details of the fabrication, electrical characterization, and profile optimization of a SiGe pFET on silicon-on-sapphire (SOS) technology. The results show that the SiGe pFETs have higher low-field mobility (/spl mu//sub eff/), transconductance (g/sub m/), and cutoff frequency (f/sub T/) than a comparable Si pFET. At low temperature (85 K), a secondary peak is observed in the linear g/sub m/ of the SiGe pFETs and is attributed to hole confinement in the SiGe channel. The effect of reducing the SOS film thickness on the mobility and short-channel performance is studied. A low-frequency noise study shows significant improvement in the SiGe pPETs over comparable Si pFETs, and is attributed to a lower sampling of interface trap density caused by the band offset at the oxide interface due to SiGe. Drain Induced Back Channel Inversion (DIBCI) is shown to occur in short gate length devices, resulting in high off-state leakage current through conduction at the back silicon-sapphire interface. The paper also discusses important optimization issues in the design of 0.25-/spl mu/m gate length SiGe pFETs. A novel structure is proposed which optimizes the threshold voltage, maximizes hole confinement gate voltage range and cutoff frequency, while at the same time minimizing DIBCI to make the design usable to gate lengths as short as 0.25 /spl mu/m.

High-performance polycrystalline SiGe thin-film transistors using Al2O3 gate insulators

The use of aluminum oxide as the gate insulator for low temperature (600/spl deg/C) polycrystalline SiGe thin-film transistors (TFTs) has been studied. The aluminum oxide was sputtered from a pure aluminum target using a reactive N/sub 2/O plasma. The composition of the deposited aluminum oxide was found to be almost stoichiometric (i.e., Al/sub 2/O/sub 3/), with a very small fraction of nitrogen incorporation. Even without any hydrogen passivation, good TFT performance was measured an devices with 50-nm-thick Al/sub 2/O/sub 3/ gate dielectric layers. Typically, a field effect mobility of 47 cm/sup 2//Vs, a threshold voltage of 3 V, a subthreshold slope of 0.44 V/decade, and an on/off ratio above 3/spl times/10/sup 5/ at a drain voltage of 0.1 V can be obtained. These results indicate that the direct interface between the Al/sub 2/O/sub 3/ and the SiGe channel layer is sufficiently passivated to make Al/sub 2/O/sub 3/ a better alternative to grown or deposited SiO/sub 2/ for SiGe field effect devices.

A deep submicron Si/sub 1-x/Ge/sub x//Si vertical PMOSFET fabricated by Ge ion implantation

We report a deep submicron vertical PMOS transistor using strained Si/sub 1-x/Ge/sub x/ channel formed by Ge ion implantation and solid phase epitaxy. These vertical structure Si/sub 1-x/Ge/sub x//Si transistors can be fabricated with channel lengths below 0.2 /spl mu/m without using any sophisticated lithographic techniques and with a regular MOS process. The enhancement of hole mobility in a direction normal to the growth plane of strained Si/sub 1-x/Ge/sub x/ over that of bulk Si has been experimentally demonstrated for the first time using this vertical MOSFET. The drain current of these vertical MOS devices has been found to be enhanced by as much as 100% over control Si devices. The presence of the built-in electric field due to a graded SiGe channel has also been found to be effective in further enhancement of the drive current in implanted-channel MOSFET's.

Device parameter optimization of strained Si channel SiGe/Si n-MODFET's using a one-dimensional charge control model

We have simulated the strained Si channel SiGe n-MODFET structure using a one-dimensional (1-D) self-consistent Schroedinger-Poisson charge control model. The quantum confinement effect has been investigated and key transistor parameters have been optimized for maximum f/sub T/. It has been found that the doping concentration into the donor layer and the Ge mole fraction of the SiGe layers should be as high as possible, provided that the doping diffusion and the avalanche breakdown are under control and the crystalline quality of the epilayers is not significantly degraded. The optimum channel thickness was found to be between 5 and 7.5 nm. In addition, it has been shown that the thickness of the donor layer should be used for threshold voltage adjustment rather than for f/sub T/ improvement.

Study of Hall and effective mobilities in pseudomorphic Si1−xGex p-channel metal–oxide–semiconductor field-effect transistors at room temperature and 4.2 K

A study of several Si0.8Ge0.2 p-channel heterostructures with self-aligned poly-Si metal–oxide–semiconductor gates were carried out. A novel fabrication process was developed which is compatible with the strained Si/SiGe system, and it has allowed Hall and resistivity measurements to be performed at room temperature and at 4.2 K. The structures were numerically modelled to calculate the charge distribution with temperature and with gate voltage and the results have shown good agreement with experiment. Hall measurements at 4.2 K have shown consistent SiGe channel Hall mobility enhancements of ×3 over the SiO2/Si channels in the same devices. Room temperature effective mobilities were measured for a buried Si0.8Ge0.2 p-channel metal–oxide–semiconductor field-effect transistor heterostructure using capacitance–voltage measurements to calculate the carrier density. Mobilities are consistently over 300 cm2/V s and the low temperature studies, together with measurements of comparable modulation doped heterostructures, and secondary-ion-mass spectroscopy depth profiles suggest that this mobility is at present limited by the quality and proximity of the SiO2/Si interface.

Growth and electron effective mass measurements of strained Si and Si 0.94Ge 0.06 on relaxed Si 0.62Ge 0.38 buffers grown by rapid thermal chemical vapor deposition

We report the growth and the electron cyclotron resonance measurements of n-type Si/Si 0.62Ge 0.38 and Si 0.94Ge 0.06/Si 0.62Ge 0.38 modulation-doped heterostructures grown by rapid thermal chemical vapor deposition. The strained Si and Si 0 94Ge 0.06 channels were grown on relaxed Si 0.62Ge 0.38 buffer layers, which consist of 0.6 μm uniform Si 062Ge 0.38 layers and 0.5 μm compositionally graded relaxed SiGe layers from 0 to 38% Ge. The buffer layers were annealed at 800 °C for 1 h to obtain complete relaxation. A 75 Å Si(SiGe) channel with a 100 Å spacer and a 300 Å 2 × 10 19 cm −3 u-type supply layer was grown on the top of the buffer layers. The cross-sectional transmission electron microscope reveals that the dense dislocation network is confined to the buffer layer, and relatively few dislocations terminate on the surface. The planview image indicates the threading dislocation density is about 4 × 10 6 cm −2. The far-infrared measurements of electron cyclotron resonance were performed at 4 K with the magnetic field of 4–8 T. The effective masses determined from the slope of the center frequency of the absorption peak versus applied magnetic field plot are 0.203 m 0 and 0.193 m 0 for the two dimensional electron gases in the Si and Si 0.94Ge 0.06 channels, respectively. The Si effective mass is very close to that of a two dimensional electron gas in an Si MOSFET (0.198 m 0). The electron effective mass of Si 0.94Ge 0.06 is reported for the first time and is about 5% lower than that of pure Si.

Study of uniform and graded SiGe channel heterojunction p-MOSFETs using Monte Carlo simulation

We report on a Monte Carlo analysis of a SiGe p-channel 0.18 μm MOSFET. This work emphasizes the influence of the Ge channel profile on device performances. A uniform Ge profile with 0.3 Ge mole fraction provides a good hole confinement in the channel, with a reduction of the surface scattering at oxide interface and an improvement of the hole transport properties in SiGe. A graded Ge profile (0% at the bottom of the channel to 30% at the top) provides a further improvement due to the hole confinement closer to the gate. A better gate-control of the drain current is achieved leading to an increased transconductance, a reduced drain-induced-barrier-lowering, a reduced subthreshold slope, and a better saturation behavior.

Electron beam induced damage of silicon germanium

The damage to modulation-doped pseudomorphic SiGe channels was investigated for a typical 40 keV electron beam lithography resist technique and also a high resolution 300 keV direct write SiO2 patterning technique. Annealing studies on the irradiated samples were also performed. Results show that the 40 keV technique only creates insignificant amounts of surface damage while the 300 keV technique creates significant damage even at deep, strained SiGe quantum wells. Annealing can be used to reduce the 40 keV damage but has little effect on the 300 keV damage. A number of narrow channel devices were fabricated to assess the range of the 300 keV damage.

Thermal emission of holes from confined levels in strained SiGe channel p-MOSFETS

We report preliminary results of current transient spectroscopy (CTS) investigations performed on a buried strained Si 0.85Ge 0.15 channel p-MOSFET structure. Measurements give an activation energy E a=83±10 meV. In these structures the fundamental confined level energy E 0=69 meV. We propose that the above activation energy corresponds to thermal emission of holes from E 0 since the summation E a+ E 0=152±20 meV is in good agreement with the measured valence band discontinuity (Δ E V) values reported in the literature.

Current distributions in silicon–germanium p-MOSFETs

Simulations of the current distributions in Si–Ge p–MOSFETs are presented for Si–Ge channel designs that have a triangular or a uniform Ge profile. The distributions of current show why the triangular design is better than the uniform Ge profile. Contributions to the transconductance in both designs are dominated by the Si–Ge channel in the −0.5 to −1.5 V gate-voltage range but the contribution to the device performance from the current parallel to the top oxide/Si interface dominates the response by −2.5 V.

Strain relaxation and dislocations in SiGe/Si structures

Epitaxially grown lattice mismatched structures are of increasing importance for microelectronic and optoelectronic devices and circuits fabricated using a variety of semiconducting materials. For some applications, the strain in the epitaxial layers is intentionally relieved by the introduction of misfit dislocations, and the film has an in-plane lattice parameter close to that of the bulk material. For example, a fully relaxed Si0.7Ge0.3 layer is required as a buffer layer for high mobility field effect transistors having strained Si or strained SiGe channels. In this case it is necessary to control the growth conditions and the design of the structure so as to minimize the density of dislocations threading through device layers grown on top of the relaxed buffer layer. The need to prevent strain relaxation in thin layers or to control the density and distribution of defects in intentionally relaxed structures has lead to extensive research on strain relaxation mechanisms and on the properties of the defects which are required to relieve the strain. This article will focus on recent work on strain relaxed SiGe/Si structures. Two different relaxation mechanisms occurring at low mismatch strain and low growth temperature will be discussed, and the characteristics of step-graded buffer layer structures will be reviewed. Effects of dislocations on the electronic properties of relaxed SiGe layers will also be discussed.

Operation of SiGe channel heterojunction p-MOSFET

We report a Monte Carlo analysis of SiGe p-MOSFET in comparison with conventionally designed Si p-MOSFET. The purpose of our study is to quantify the contribution in device performance enhancement of the separation of holes from rough Si/SiO 2 interface and of the SiGe transport properties. In SiGe p-MOSFET, the effective channel mobility is increased by a factor 2.6 with 60% of this improvement due to the confining of holes in a potential well. The device performances I D, g m , and f T are improved by at least 55% only due to the strain-induced lowering of the hole effective mass in SiGe.

Thermal stability of undoped strained Si channel SiGe heterostructures

We have investigated the thermal stability of Si/SiGe n-channel heterostructures. To eliminate the complication of dopant diffusion, we have fabricated undoped Si/SiGe heterostructure Hall effect devices. With no modulation doping used in our structures, the electron concentration in the strained Si channel is controlled from a back gate. Our devices show high electron mobility of up to 19 500 cm2/V s at 77 K and are stable with negligible 77 K mobility reduction after anneals at 800 °C for 30 min and at 950 °C for 3 min. These results conform well with a simulation of the diffusion of Ge into the Si channel.

The Profile Design of Strained Sige-Channel P-Type Modulation Doped Fet

ABSTRACTTo improve the performance of p-type SiGe-channel FEPs is important for Si-based high-speed/high-frequency applications. This work discusses the design of germamium profiles in the strained Si1−xGex channel region of p-type SiGe modulation doped FET's and studies its effect on device performance. Two-dimensional device simulator is used to simulate the large-signal device performance for various Ge distributions including triangular, trapezoidal, and flat profiles. In particular, the thickness of the strained SiGe channel layer is 15 nm and a 5 ran thick Si cap layer is on top of the channel. It is found that with the same integrated Ge content in the strained channel, graded Ge profiles lead to higher transconductances and larger threshold voltage windows than those of flat profiles, due to deeper potential wells and better carrier confinement ability. For triangularly graded profiles, the peak position must be located in the upper half portion of the channel layer to result in superior performance. By adding more Ge to extend the peak region, triangular profiles become trapezoidal ones. However, more Ge content does not necessarily produce better performance. If the well depth of trapezoidal profile is the same as that of triangular profile and if the trapezoid plateau begins at the same position as that of triangle peak, the device performance is almost the same for both profiles.