The Profile Design of Strained Sige-Channel P-Type Modulation Doped Fet

Abstract

ABSTRACTTo improve the performance of p-type SiGe-channel FEPs is important for Si-based high-speed/high-frequency applications. This work discusses the design of germamium profiles in the strained Si1−xGex channel region of p-type SiGe modulation doped FET's and studies its effect on device performance. Two-dimensional device simulator is used to simulate the large-signal device performance for various Ge distributions including triangular, trapezoidal, and flat profiles. In particular, the thickness of the strained SiGe channel layer is 15 nm and a 5 ran thick Si cap layer is on top of the channel. It is found that with the same integrated Ge content in the strained channel, graded Ge profiles lead to higher transconductances and larger threshold voltage windows than those of flat profiles, due to deeper potential wells and better carrier confinement ability. For triangularly graded profiles, the peak position must be located in the upper half portion of the channel layer to result in superior performance. By adding more Ge to extend the peak region, triangular profiles become trapezoidal ones. However, more Ge content does not necessarily produce better performance. If the well depth of trapezoidal profile is the same as that of triangular profile and if the trapezoid plateau begins at the same position as that of triangle peak, the device performance is almost the same for both profiles.