Characterization and profile optimization of SiGe pFETs on silicon-on-sapphire

Abstract

We present the details of the fabrication, electrical characterization, and profile optimization of a SiGe pFET on silicon-on-sapphire (SOS) technology. The results show that the SiGe pFETs have higher low-field mobility (/spl mu//sub eff/), transconductance (g/sub m/), and cutoff frequency (f/sub T/) than a comparable Si pFET. At low temperature (85 K), a secondary peak is observed in the linear g/sub m/ of the SiGe pFETs and is attributed to hole confinement in the SiGe channel. The effect of reducing the SOS film thickness on the mobility and short-channel performance is studied. A low-frequency noise study shows significant improvement in the SiGe pPETs over comparable Si pFETs, and is attributed to a lower sampling of interface trap density caused by the band offset at the oxide interface due to SiGe. Drain Induced Back Channel Inversion (DIBCI) is shown to occur in short gate length devices, resulting in high off-state leakage current through conduction at the back silicon-sapphire interface. The paper also discusses important optimization issues in the design of 0.25-/spl mu/m gate length SiGe pFETs. A novel structure is proposed which optimizes the threshold voltage, maximizes hole confinement gate voltage range and cutoff frequency, while at the same time minimizing DIBCI to make the design usable to gate lengths as short as 0.25 /spl mu/m.