SiGe Channel Research Articles

(Invited) Gate Stacks for Silicon, Silicon Germanium, and III-V Channel MOSFETs

High-k gate dielectrics such as HfO2 and metal gate electrodes such as TiN have been deployed across a wide range of CMOS logic products in both the low-power (e.g., mobile) and the high-performance (e.g., server) space. Available device geometries include planar field-effect transistors on bulk Si, on partially depleted silicon-on-insulator (PDSOI), and on fully depleted SOI (FDSOI), as well as FinFETs. During the decade-long effort leading up to successful high-k/metal gate (HKMG) implementation, much has been learnt about the fundamental materials science underlying such gate stacks. Yet, research continues in order to ensure continued circuit density and performance scaling.After reviewing the gate-first and gate-last (or replacement gate) approaches to HKMG implementation, I will discuss device challenges that can be resolved by materials engineering on the atomic scale. A prime example is the threshold voltage (Vt) challenge, which is caused by charged oxygen vacancies in hafnium-based gate dielectrics formed at elevated temperatures, thus increasing pFET Vt. These vacancies can be filled by lateral or top-down oxidation. As an alternative, additional Vt-setting techniques can be employed, such as metal oxide capping layers (e.g., Al2O3 or La2O3 for pFET and nFET, respectively) that form permanent electrical dipoles, or SiGe channels (cSiGe) which modulate the band offsets while additionally providing a welcome hole mobility boost. A second example is continued equivalent oxide thickness (EOT) scaling. We have developed the approach of metal-gate-induced remote oxygen scavenging, which results in a thinning of the SiO2 layer at the high-k/channel interface. In this way, EOT of 0.4-0.5 nm can be reached for both nFET and pFET. I will in particular discuss our recent results on aggressive cSiGe pFET scaling (Fig. 1), including the dependence of hole mobility (Fig. 2) and of negative bias temperature instability (NBTI) reliability on EOT and thus on interfacial SiO2thickness [1].In the second part of my talk, I will show that HKMG not only provides the well-known gate-length scaling benefit through improved electrostatics, but it can also directly enable aggressive device pitch and density scaling through borderless (semi-self-aligned) source-drain (S/D) contacts [2]. Conventional gate-first high-k/metal gate (HKMG) CMOS technologies employ metal-inserted poly-Si stacks (MIPS) such as a-Si/TiN, where the amorphous Si serves as a precursor for low-sheet-resistance (Rs) self-aligned NiSi on the gates and as an oxygen barrier preventing high-k/Si interfacial SiO2 growth. A full metal gate (FMG, Fig. 3), instead containing a deposited low-Rs metal layer, can be encapsulated in a dielectric resistant to the S/D contact etch, resulting in borderless contacts. We have developed two FMG electrodes based on TiSix/TiN and W/TaMN/TiN (M = oxygen scavenging metal). With both FMG on Hf-based gate dielectrics, Si channel nFET and SiGe channel pFET parametrics and reliability similar to those of poly-Si/TiN control devices are achieved, with good EOT scalability [3,4].Finally, I will provide an outlook on high-k gate dielectrics for high-mobility III-V channel materials. Specifically, I will compare three interface approaches to InGaAs channel nFET gate stack formation. The first is based on direct high-k deposition onto InGaAs, while the other two approaches rely on the insertion of an amorphous Si or an epitaxial InP capping layer to passivate the InGaAs. The impact of such caps on interface trap density and scalability will be discussed.[1] M.M. Frank et al., ECS Solid State Lett. 2, N8 (2013).[2] S.-C. Seo, et al., VLSI, p. 36 (2011).[3] M. M. Frank et al., as discussed at SISC 2011.[4] M. M. Frank et al., as discussed at SISC 2013..

3D Simulation of Heavy-Ion Induced Charge Collection in Sub-100nm MOS-FETs Using Strained Silicon-Germanium

Single event transient of a PMOS using strained Silicon-Germanium in a sub-100nm bulk process is studied by 3D TCAD simulation. The impact of bias voltage, temperature, LET, and struck position on SET is considered. Our simulation results demonstrate that bias voltage in the range 0.8 to 1.2V greatly influence the amplitude of SET current. Temperature has a stronger influence on a SiGe channel PMOS than a Si-channel PMOS. Both SET current duration and total collection charge increase as LET increases, and SET current duration and total collection of a SiGe channel PMOS are larger than that of Si channel PMOS. These simulation results are beneficial to the space application of SiGe circuits.

(Invited) Material Engineering for 7nm FinFETs

Design rules and several candidate channel materials are explored for the 7nm technology node. FinFET transistor architecture is chosen, and the analysis is performed using 3D modeling tools, including ballistic transport, Schrodinger-driven quantization, and band-to-band tunneling leakage. The comparative analysis of Si, SiGe, Ge, GaAs, InGaAs, and InAs channel materials points to InGaAs with more than 80% Ga content as the best candidate for low power applications at 7nm design rules.

(Invited) Gate Stacks for Silicon, Silicon Germanium, and III-V Channel MOSFETs

High-k gate dielectrics such as HfO2 and metal gates such as TiN have been deployed across a wide range of silicon-based CMOS logic products. In some gate-first technologies, SiGe channels (cSiGe) have been implemented simultaneously for threshold voltage control in p-channel metal-oxide-semiconductor field-effect transistors (pMOSFET). Herein, we review aspects related to the impact of high-k/channel interfacial layers on Si, SiGe, and III-V gate stack quality and device performance. First, we review remote oxygen scavenging approaches for interfacial SiO2 thinning in HfO2/Si nFET and HfO2/cSiGe pFET devices. We show that they allow equivalent oxide thickness (EOT) to be reduced to 0.4-0.5 nm, and we discuss device performance and reliability tradeoffs that may limit continued EOT scaling. For later technology nodes, high-carrier-mobility III-V semiconductors channels such as InGaAs are under consideration. We summarize three high-k/InGaAs channel interface approaches: Direct high-k deposition, Si capping, and InP capping.

Impact of stress induced by stressors on hot carrier reliability of strained nMOSFETs

In this study, the nMOSFETs with contact-etch-stop-layer (CESL) stressor and SiGe channel have been fabricated with a modified 90 nm technology. The performance of nMOSFETs has been measured. And the hot carrier reliability of the SiGe-channeled nMOSFETs with various CESL nitride layers has also been extensively studied. In addition, the impact of stress induced by CESL stressor and SiGe-channel on hot-carrier reliability of the strained nMOSFETs has been analysed through experimental investigation. The shift in threshold voltage (Δ V th ) vs. stress time ( t ) under different stress temperatures was measured. Furthermore, according to the reliability results, both the interface states ( N it ) and oxide trapped charges ( N ot ) increased after hot-carrier stress. With regard to the hot-carrier reliability, for all stress conditions the degradation of strained nMOSFETs with compressive CESL stressor is more serious than the degradation of those with tensile CESL stressors. The nMOSFET devices with tensile CESL have better performance and hot-carrier reliability than those with compressive CESL. Moreover, it is suggested that the CESL-induced damages ( N it ) located at the interface between gate dielectric and underlying channel be responsible for the hot-carrier reliability.

Mobility Enhancement and Gate-Induced-Drain-Leakage Analysis of Strained-SiGe Channel p-MOSFETs with Higher-κ LaLuO3 Gate Dielectric

A strained-SiGe p-channel metal-oxide-semiconductor-field-effect transistors (p-MOSFETS) with higher-κ LaLuO3 gate dielectric was fabricated and electrically characterized. The novel higher-κ (κ∼30) gate dielectric, LaLuO3, was deposited by molecular-beam deposition and shows good quality for integration into the transistor. The transistor features good output and transfer characteristics. The hole mobility was extracted by the splitting C—V method and a value of 200cm2/V·s was obtained for strong inversion conditions, which indicates that the hole mobility is well enhanced by SiGe channel and that the LaLuO3 layer does not induce additional significant carrier scattering. Gate induced drain leakage is measured and analyzed by using an analytical model. Band-to-band tunneling efficiencies under high and low fields are found to be different, and the tunneling mechanism is discussed.

Characteristics and hot-carrier effects of strained pMOSFETs with SiGe channel and embedded SiGe source/drain stressors

The embedded SiGe source/drain (S/D) stressor applies the lattice mismatch between silicon and germanium atoms making silicon channel generate compressive strain in the surface channel. The compressive strain enhances hole mobility due to raising the weighting factor of the light hole contribution, causing the improvement of the pMOSFETs performance. Previous reports have investigated the effects of pMOSFETs with embedded SiGe S/D stressor. But, devices incorporated with biaxial strain and embedded SiGe S/D have not been clearly investigated. In this work, not only were the characteristics of devices containing biaxial strain and embedded SiGe S/D stressor with different channel lengths exposed, but the channel-hot-carrier (CHC) effect in short-channel pMOSFETs was also followed with interest. The experimental results show that the biaxial strain achieved higher carrier mobility in long channel. However, this strain reduces its mobility enhancement effect when the channel length becomes shorter. In addition, the embedded SiGe S/D stressor enhances the carrier mobility by increasing compressive strain in the short channel. After the CHC test for pMOSFETs with these two processes, the saturation current of the embedded SiGe S/D pMOSFETs degraded 5.5%, which was more serious than 4.2% degradation of biaxial-strain devices. It is presumable that embedded SiGe S/D strain induces more interface states or trap generation located at source/drain junction.

Comparison of NMOSFET and PMOSFET Devices That Combine CESL Stressor and SiGe Channel

Strained-Si technology could enhance the carrier mobility and improve the device performance. Contact-etch-stop-layer (CESL) structure with different stress and SiGe channel was fabricated with 90-nm technology. The electrical properties of N and PMOSFET devices combining CESL and SiGe channel were investigated. The short channel effects (SCE), such as drain-induced barrier lowering (DIBL), were also studied. Moreover, the stress contour in the SiGe channel has been simulated with TCAD to understand the relationship between stress distribution and device performance for different CESL structures. It is observed that the stress in the channel region was independent of the type of N or PMOSFET devices, but it was dependent on the CESL type and channel length. Based on the experimental and simulation results, it is confirmed that the device performance is associated with the stress in the channel, and the approach of CESL stressor and SiGe channel is shown to effectively improve the mobility of NMOSFETs and PMOSFETs.

NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack

Due to a significantly reduced negative-bias temperature instability (NBTI), (Si)Ge channel pMOSFETs are shown to offer sufficient reliability at ultrathin equivalent oxide thickness. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric stack is ascribed to a reduced availability of interface precursor defects and to a significantly reduced interaction of channel carriers with gate dielectric defects due to a favorable energy decoupling. Owing to this effect, a significantly reduced time-dependent variability of nanoscale devices is also observed. The superior reliability is shown to be process and architecture independent by comparing both our results on a variety of Ge-based device families and published data of other groups.

Hole Transport in Strained and Relaxed SiGe Channel Extremely Thin SOI MOSFETs

We report experimental data comparing aggressively scaled SiGe channel extremely thin SOI MOSFETs with either relaxed or strained channels. The analysis clearly demonstrates that without strain, SiGe channel delivers performance comparable with relaxed Si devices. Significantly higher performance is observed only in compressively strained SiGe channel devices, especially in narrower devices where the transverse component of the strain is partially relaxed.

Performance Dependence on Width-to-Length Ratio of Si Cap/SiGe Channel MOSFETs

This paper measures the n- and p-MOSFETs fabricated through 65-nm high- k/metal gate CMOSFET process flow. The [110] channels of the Si cap on SiGe with different width (W) and length (L) ratios were compared with Si-only channels. The results show that a high W-L ratio in the [110] n-channel can alleviate the degradation of biaxial compressive stress. Meanwhile, a low W-L ratio in the p-channel can improve the performance; however, the ratio should at least be below two in this paper. The dominance of the longitudinal or transverse configurations successfully explains this phenomenon because of the reliance of the different levels of piezoresistance coefficient on the channel orientation. The threshold voltage shifts versus the W-L ratio in the p-channel is in agreement with the result. The result is verified by a quantitative current comparison at a high bias in the n-/p-channels between the strained SiGe and Si-only channels, which shows that an extreme W-L ratio in the original biaxially strained SiGe channel can result in longitudinal or transverse strain, thereby leading to different levels of performance degradation/improvement.

Improved Operation Characteristics in Charge-Trapping Flash Memory Devices With Engineered Dielectric Stack, Sige and Junctionless Poly-Si Channels

not Available.

(Invited) Improved Operation Characteristics in Charge-Trapping Flash Memory Devices with Engineered Dielectric Stack and SiGe Channel

Programming and retention characteristics of charge-trapping (CT) non-volatile memory (NVM) devices can be enhanced by inserting Al2O3 between Si3N4 and HfO2 as the charge-trapping layer. This is because most of the injecting charges are trapped at Si3N4/Al2O3 interface and Al2O3 also provides a high barrier for electron detrapping. In addition, Compare to those with conventional Si-channel, both programming and erasing speeds are significantly improved by employing a Si0.7Ge0.3 buried channel. Satisfactory retention and excellent endurance characteristics up to 106 P/E cycles with 4.1 V memory window show that the degradation on reliability properties, if it exists, is negligible when SiGe buried channel is introduced.

Analysis of the Performance of n-Type FinFETs With Strained SiGe Channel

This paper reports a simulation study investigating the drive current of a prototypical SiGe n-type FinFET built on a relaxed SiGe substrate for different values of the Ge content <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> in the Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(1-</sub> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> )Ge <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> active layer. To this purpose, we performed strain simulations, band-structure calculations, and multisubband Monte Carlo transport simulations accounting for the effects of the Ge content on both the band-structure and the scattering rates in the transistor channel. Our results suggest that the largest on-current may be obtained with a simple Si active layer, because of the beneficial strain induced by the SiGe substrate. A SiGe channel instead is less performing because of strain relaxation and alloy scattering.

Phenomena of n-type metal-oxide-semiconductor-field-effect-transistors with contact etch stop layer stressor for different channel lengths

In this paper, n-type metal-oxide-semiconductor-field-effect-transistors (nMOSFETs) combining contact etch stop layer (CESL), SiGe channel, and Si-cap have been fabricated. The simulation results and electrical properties have also been investigated and indicated that the CESL type (tensile or compressive) or channel length (short or long) has a significant effect on the stress distribution of the channel. This is important because the stress in the channel region affects the carrier mobility and therefore the device performance. In order to verify the simulation results, the electrical properties such as mobility and output characteristics have been measured. According to the output characteristics, as channel length is 0.11μm, the tensile CESL can enhance the performance of nMOSFETs. However, the improved trend is inverted when the channel length increases. On the other hand, we have also compared the threshold voltage (Vt) roll-off and subthreshold swing (SS) for different structures. The results show that the devices exhibit a worse Vt roll-off when CESL is adopted and SS degrades more when compressive stress is induced in the channel.

Substrate dependent mobility and strain effects for silicon and SiGe transistor channels with HKMG first stacks

The impact of compressive and tensile stress on CMOS performance of high-k/metal-gate (HKMG) transistors is studied for 〈100〉 and 〈110〉 oriented silicon and SiGe channels. The (100)/〈110〉 channel direction is found to be more stress sensitive for both N- and PMOS whereas the (100)/〈100〉 oriented transistor has a higher initial hole mobility. These results recommend to use the (100)/〈110〉 channel orientation for high performance application due to the high drive current gain and (100)/〈100〉 channel orientation for low power/low cost applications where no stress elements are included to ease the overall process complexity and to decrease costs. SOC level test design implementations show consistent yield as well as improved performance.

Deposited ALD SiO2 High-k/Metal Gate Interface for High Voltage Analog and I/O Devices on Next Generation Alternative Channels and FINFET Device Structures

A highly reliable SiO2 deposited by atomic layer deposition (ALD) as a gate dielectric interface layer with high-k/metal gate (HKMG) in high voltage I/O field effect transistor (FETs) for advanced technologies has been demonstrated. Improved process control, better gate oxide conformality, superior dielectric reliability (over CVD SiO2), and equivalent uniformity and reliability compared to thermal oxide proves its usefulness for FinFET/ETSOI I/O devices. In addition, use of ALD SiO2 with novel interface layer results in reduced interfacial regrowth on SiGe channel, which when coupled with post deposition nitridation and annealing optimization for optimal performance, is an attractive oxide optimization option for alternate channel architectures.

Impact of Ge proportion on advanced SiGe bulk P-MOSFET matching performances

In this work, P-MOS transistors of advanced bulk technology integrating high K/metal gate and SiGe channel are considered. An exhaustive study of threshold voltage (Vt), current gain factor (β), and drain-current (Id) mismatches with different Ge proportions in the channel is performed, in linear regime, for transistors with and without pocket implants. A comparison between channels with and without Germanium and with different proportions of Germanium is considered. A global improvement of P-MOS transistors electrical parameters mismatch is observed with the introduction of Ge in the channel. Some explanations for this improvement with the introduction of Ge are proposed.

High-Performance Ultrathin Body c-SiGe Channel FDSOI pMOSFETs Featuring SiGe Source and Drain: $V_{\rm th}$ Tuning, Variability, Access Resistance, and Mobility Issues

We report on ultrascaled (LG = 23 nm) compressively strained SiGe-based FDSOI pMOSFET with ultrathin body. The devices have been fabricated using a high-K metal gate (TiN/HfSiON) process flow. SiGe channels (3.4 nm) have been epitaxially grown on 3-nm thick 300-mm SOI wafers and combined with embedded Si0.7Ge0.3(:B) raised source and drain (RSD) for Vth,p tuning and smart strain management. Indepth electrical characterizations point out the +120-mV Vth,p tuning, the excellent short-channel, and DIBL control (similar to SOI reference), and show for the first time extremely low variability for SiGe-based FD pMOSFETs. Furthermore, we investigate hole-transport properties as a function of gate length and temperature and demonstrate 60% Raccess reduction with SiGe RSD and +330% mobility enhancement at 23-nm gate length with respect to 7-nm thick SOI reference.

Performance Enhancement on p-Channel Charge-Trapping Flash Memory Device With Epitaxial Si/Ge Super-Lattice Channel

Operation characteristics of p-channel ${\rm TaN}/{\rm Al}_{2}{\rm O}_{3}/{\rm HfO}_{2}/{\rm HfAlO}_{2}/{\rm SiO}_{2}/{\rm Si}$ MAHOS-type nonvolatile memory devices with an epitaxial Si/Ge super-lattice (SL) channel are investigated in this letter, where the SL channel is characterized with good crystal structure and high thermal stability. Remarkable improvement on programming and erasing speeds is observed, as compared to those with SiGe channel. Furthermore, the degradation on reliability properties of retention and endurance is negligible for the device with employing a SL channel.