SiGe Channel Research Articles

Characterization and modelling of layout effects in SiGe channel pMOSFETs from 14 nm UTBB FDSOI technology

The introduction of strained channel is mandatory to achieve high performance in Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI) technology. Especially, compressive SiGe channel has been demonstrated to enhance hole mobility and therefore pMOSFETs drive currents. At the same time, the performance gain induced by this mechanical stressor comes along with layouts effects. In this study, we characterize experimentally the impact of the active region dimensions and shape on the threshold voltage and linear drain current of SiGe channel pMOSFETs directly on insulator fabricated for the 14nm technology node. The pMOS threshold voltage increases by 105mV for a gate-to-STI distance of 80nm compared to 980nm while IODLIN decreases by 51%. An analytical model is proposed to reproduce the layout dependences. The model is based on the stress profile, taking into account both the stress from the SiGe channel and from SiGe source/drain. It reproduces the experimental data with a good accuracy in the cases of symmetric and asymmetric layouts, provided a typical relaxation length of 112nm is used. Finally, a special attention is paid on multifinger transistors, since they are widely used in standard cells designs.

Design and analysis of nanowire p-type MOSFET coaxially having silicon core and germanium peripheral channel

In this work, a nanowire p-type metal–oxide–semiconductor field-effect transistor (PMOSFET) coaxially having a Si core and a Ge peripheral channel is designed and characterized by device simulations. Owing to the high hole mobility of Ge, the device can be utilized for high-speed CMOS integrated circuits, with the effective confinement of mobile holes in Ge by the large valence band offset between Si and Ge. Source/drain doping concentrations and the ratio between the Si core and Ge channel thicknesses are determined. On the basis of the design results, the channel length is aggressively scaled down by evaluating the primary DC parameters in order to confirm device scalability and low-power applicability in sub-10-nm technology nodes.

Low Power FDSOI Technology and Devices for RF Applications

: We report RF Characteristics in a Low Power High Performance Ultra-thin Body and Box (UTBB) FDSOI technology. The technology features Si-Channel nFETs and SiGe-Channel pFETS, a gate first HiKMG stack with a gate length (LG) of 20nm, BOX thickness (TBOX) of 20nm and is similar to that described previously[1]. The use of the backgate gate is shown to dynamically change the operating range and expand the dynamic range for RF. Competitive f T s are reported for nFETs. The thin body architecture demonstrates high self gain. The technology is shown to be well optimized for applications like IoT where low power and RF performance are a premium. UTBB FDSOI technology offers a superior technology for IoT because of the low power performance of the technology and RF performance. A TEM micrograph of the nFET silicon channel and pFET SiGe channel is sown in Figure 1. The high K metal Gate, thin channel silicon and SiGe channel, and raised source drains architecture can be seen clearly seen in the tem Micrographs. The FDSOI transistor has a back gate electrode which provides a unique capability to shift the threshold voltage and operating point of the transistor. This capability is shown in Fig. 2 and Fig. 3 which is a linear plot of Id versus Vgs for Vbg = -2, 0, and 2 Volt bias for the nFET and pFET respectively. The Drain current is well behaved and is shown to shift as the back bias changes the threshold voltage. The digital low power performance of the technology is derived by the absence of drain to source leakage path and a steep subthreshold slope. The thin silicon channel and SiGe channel of 7nm prevents a leakage path and provides a fully depleted channel with superior electrostatics The technology Idsat current reaches 900μA/μm and 670μA/μm for NFET and PFET respectively, at off current (Ioff) of 100nA/μm and Vdd of 0.8V. The Log Id vs Vgs plots for the nFET and pFET are shown in Fig. 4 at a gate length of 20nm. The subthreshold slope of 85 mV/decade demonstrates the steep subthreshold that enables a low threshold voltage to be maintained with low leakage. The output characteristic for nFET Lg=30nm is shown in Fig. 5. The flat shape of the curve also indicates both nFET has low gDs. Out conductance curves (not shown here) show no roll-off at high Vd indicating little if any self heating. In this FDSOI technology the nFET tansconductance reaches gM ~ 1.8mS/um at Lg=20nm and the pFET transconductance reaches gMsat ~ 1.2.mS/um. The gMsat operating point may be adjusted with back gate bias as is shown in Fig. 6 for the nFET with a back gate bias with -2, 0, and 2 volts. The ratio of gMsat/gDS is the self gain wich is enhanced in fully depleted FDSOI technology. The self gain for the nFET is shown in Figure 7 with a back gate bias with -2, 0, and 2 volts. RF Performance is extremely important for IoT and other applications. The RF simulated RF performance of the nFET achieves a peak f T of over 300 GHz as is shown in Figure 8 which plots f T vs Vgs for Vbg = -2, 0, and 2 Volts. Note how the operating point can be moved around just as in the gMsat figure by applying the appropriate back gate bias. This expanded dynamic range is also true for the pFET operation. These are the first FDSOI RF characterization results published on a 20nm Lgate HiKMG process.

(Invited) Germanium Enrichment for Planar-, Fin- and Nanowire-Channel MOSFETs Made on SOI

1. Introduction Depleted body devices such as FinFETs and Ultra-Thin Body and Buried oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) MOSFETs have emerged as architectures of choice for technology nodes where conventional planar bulk devices do not provide enough immunity against short channel effects and variability. Offering unsurpassed electrostatic control of the channel, NanoWire FETs (NWFETs)-based architectures are considered as promising successors for future nodes. In all these depleted-body architectures, the control of active power is a strong requirement. Along with supply voltage scaling, it imposes design-level power management strategies, parasitic capacitance reduction and it calls for the use of high-mobility channel materials. For p-type channels, compressively strained silicon germanium alloys (SiGe) are attractive candidates. When depleted-body devices are fabricated on SOI, local germanium enrichment can convert Si to SiGe. This fabrication sequence starts with the growth of an epitaxial SiGe layer, followed by oxidation. During the latter, the surface of the SiGe layer is converted to silicon dioxide while Ge is segregated to the lower part of the stack, which gradually becomes more Ge-rich. This paper discusses the fabrication of SiGe channel for UTBBSOI MOSFETs, FinFETs and NWFETs. It reviews the key points associated to each architecture and critical aspects related to SiGe thermal budget, critical thickness, growth rate control and crystal quality. Results highlight the interest of NWFETs for future technology nodes. 2. SiGe channel UTBB FDSOI MOSFETs The Ge enrichment technique was initially developed for the planar FDSOI architecture and in that context, it was shown that high quality uniform SiGe films can be fabricated by alternating oxidizing and diffusion steps. For a SiGe/Si initial stack of given thickness and composition, the enrichment thermal budget needs to be significantly different when it is performed on SOI or on tensile SOI (sSOI). In the last case, the film initial tensile strain slows Ge diffusion (Fig. 1-a), which can lead to Ge pile up and defect formation if process temperature is too high with respect to the peak concentration (Fig. 1-b). Defect-free SiGe layers can be obtained on sSOI by using longer diffusion steps and reducing process temperature (Fig. 1-c). 3. SiGe-channel FinFET Although Ge enrichment can produce fully-strained layers, the patterning of SiGe blanket film into finite-dimension active areas yields elastic stress relaxation. This feature is particularly attractive for the fabrication of SiGe channel FinFETs where channel configuration results in longitudinal uniaxial compression, which is most favorable to hole transport. However, this processing sequence involves the elaboration of a thick blanket SiGe layer (through Ge enrichment and epitaxial thickening). Even with optimized processing, for a targeted Fin height (SiGe thickness) of 35 nm, significant crystal quality degradation is observed by X-Ray Reciprocal Space Mapping for {113} (RSM) when the Ge fraction approaches 50% (Fig. 2-a), in agreement with literature. To overcome this limit, Ge enrichment of already patterned Si Fins was investigated. This sequence relieves the limits set by SiGe critical thickness in the vertical direction, but it also constricts the pre-enrichment SiGe growth conditions. If SiGe growth rate is strongly dependent on crystal orientation, the final Fin profile is degraded (Fig. 2-b). In contrast, Fin profile can be maintained (Fig. 2-c) when uniform SiGe thickness can be achieved on Fin sidewalls (Fig. 2-d). RSM shows that Fins with up to 50% Ge fraction exhibit no significant relaxation (Fig. 2-e). This approach is expected to be most beneficial for tall Fins. 4. SiGe-channel NWFETs W-gate NWFETs were fabricated in a gate first scheme (Fig. 3-a). This configuration combines the respective benefits of SiGe channel FDSOI MOSFETs and FinFETs in terms of SiGe crystal stability [5] and uniaxial strain. With this and excellent electrostatic integrity, significant mobility gains are demonstrated down to a gate length of 14nm (Fig. 3-b), paving the way for future energy-efficient systems. 5. Acknowledgment Part of these results was obtained in a Joint Development Program between IBM, STMicroelectronics and LETI CEA. Figure 1

(Invited) UTBB FDSOI PMOSFETs Including Strained SiGe Channels at the 14nm Technology Node and Beyond

The 28 nm Ultra-Thin Body and Buried Oxide (UTBB) Fully Depleted Silicon-On-Insulator (FDSOI) technology is in production [4]. This technology addresses both high performance and low power / low voltage applications. Indeed, a 28 nm FDSOI Processor (CPU) has been demonstrated to run at 3 GHz for a 1.3 V supply voltage (Vdd), 1 GHz for 0.6 V, still 300 MHz at 0.5 V [1]. This latter result evidences the high potential of FDSOI for Low Voltage operation, required for the next handheld, mobile or Internet-of-Things markets. The 14nm FDSOI technology extends this offer to even more performance (+50% frequency at a given dissipated power), with a 100mV supply voltage reduction [5]. For the 14nm FDSOI, we have integrated SiGe channel, which enables to achieve high biaxial compressive stress due to the lattice mismatch between Silicon and Germanium. The compressive stress enhance the hole mobility, and in turn pMOSFETs performance. In such an approach, one of the main challenges is to conserve the strain during the CMOS integration. Especially, it is well known that the patterning of SiGe leads to partial relaxation close to the active edges. This relaxation affects especially the level of stress in the channel when the dimensions of the active are small. The stress configuration becomes thus strongly layout-dependent. We have physically and electrically characterized the strain-induced layout effects in SiGe pMOSFETs built on Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI). This layout effect is reproduced by an accurate physics-based electrical model, which enable us to predict the device and design performance for various technological configurations: germanium concentration in the channel, isolation and channel process integration. In order to mitigate the impacts of the SiGe channel relaxation, we have studied two kinds of solutions. First, technological solutions are possible, leading to +21% effective current increase in short transistor at Lg=20nm gate length and in turn -15% delay reduction for ring-oscillator of 1-gate finger inverters. Secondly, we demonstrate the benefits induced by smart design layouts, enabled by process integration goodies and some layout constructs. Especially, a continuous-RX design, which consists in a long active line configuration, optimizes the stress management, maintaining longitudinal stress component while relaxing the transverse one. A 28% ring oscillator delay improvement is experimentally demonstrated at same leakage for 1-finger inverter at VDD=0.8V supply voltage [10]. This demonstrates the interest of process/design co-optimization of strain-induced layout effects. For next UTBB-FDSOI nodes below 14nm, both the electrostatics and the carrier mobility must be improved. For the hole mobility, one may think about changing the crystalline orientation of the channel and using (110)-oriented substrates. However, in terms of electronic transport, the long channel carrier mobility is no longer the most relevant electrical parameter. One should pay a great attention to i) the strain compatibility and ii) the evolution of the apparent mobility with the gate length and width. Taking them into account, for pMOSFETs, SiGe channel + SiGeB source/drain + compressive contact etch stop layers in the (100) <110> direction is the best combination. For nMOSFETs, different technological solutions have been assessed, especially based on strain memorization techniques [6-7]. Strain-SOI substrates (sSOI) is another option, which brings enough performance boost to ensure a one-node scaling (+20-30% performance increase for nMOSFETs due to tensile strain, even for narrow active regions) [8]. Finally, the gate-last integration on planar FDSOI could be another strain booster because it leverages not only a low thermal budget for EOT and a threshold voltage optimization, but also a strain improvement during the final gate formation [9].

(Keynote) FDSOI Past, Present and Future

FDSOI is quickly becoming a technology offering that can deliver next generation performance with superior low power operation at a significant cost advantage. Researchers have actively pursued alternatives to conventional bulk and PDSOI transistors for well over 10 years. However, there was not enough compelling need to change until conventional CMOS scaling dramatically slowed. Beyond the 28nm node new device architectures were needed to continue the scaling trend. FDSOI was always thought to be an attractive option since of all the alternative approaches it is the most similar to conventional bulk or PDSOI. This is mainly due to the fact that it is planar and thus much of the process and design methodology can be re used from previous nodes. On the other hand several key issues for FDSOI were known and thought to be fundamental challenges. Specifically silicon consumption, high external resistance and parasitic capacitance were identified as major hurdles. FDSOI relies upon the thin channel to control short channel effects. For example a channel thickness of approximately 6nm is required to maintain good electrostatics for a transistor with Lg=20nm. Maintaining thin silicon in the channel while still preserving silicon in the source-drain regions is a big process challenge. We have carefully optimized several key process steps including the spacer etch process to eliminate excessive silicon consumption. As shown in Fig. 1 the zero loss spacer process features a partial etch using reactive ion etching. In order to minimize silicon consumption, the spacer etch is terminated before the spacer material is completely removed from the horizontal surfaces and the dry etch cannot consume silicon. The residual spacer material is removed as part of the pre epi clean for raised source-drain. Since the wet etch for the pre-clean is highly selective to the silicon, there is no silicon consumption. High external resistance was thought to be a significant challenge for FDSOI mainly in part due to the silicon consumption from the spacer process but also from the junction formation process. Ion implantation is well known to cause damage in thin silicon even with high temperature activation anneal. The silicon damage caused by the ion implantation can also cause defective epitaxial growth during the raised source drain process. We have solved the challenge of junction formation for FDSOI by developing an implant last scheme. After the spacer module is completed the raised-source and drain is formed. Since the ion implant is done into the thick raised-source drain, the damage created is healed during the activation anneal. Parasitic capacitance is another known issue for devices with raised-source drain. We have developed a facetted epi process which eliminates a significant component of the additional parasitic capacitance caused by the raised-source drain (Fig. 2). 1 We have also developed several key elements that enable high performance FDSOI circuits. In-situ doped SiGeB for raised source-drain has been developed to reduce contact resistance and form abrupt junctions for pFETs. SiGe channel is another innovation we have developed to enable high performance by increasing hole mobility. Fig. 3 shows the benefit of the strained SiGe raised source-drain and the SiGe channel.2 FDSOI is scalable and can be used for several technology nodes. Gate length scaling for FDSOI can be accomplished by thinning the silicon. Reverse back bias can also be used to improve short channel effects and enable scaling. Figure 4 shows the improvement in short channel control as the silicon is thinned down to 3.5nm Remarkably the external resistance of the devices is not compromised as evidenced by the Ion vs Ioff comparison to devices with 6nm channel thickness. The same figure also shows the improvement in electrostatic behavior with reverse back bias.3 Additional improvements in FDSOI performance can be achieved by strained silicon on insulator technology. Figure 5 shows the benefit of the strained silicon channel for nFETs.4 Table 1 shows a comparison of state of the art FDSOI research transistors to FinFETs.5It is interesting to note that the FDSOI devices can achieve competitive drive currents at dramatically shorter gate-lengths thereby improving circuit performance. It is also interesting to note the FinFETs are normalized to the footprint which is 30% greater than the effective channel width. References K. Cheng et. al. IEDM 2010.K. Cheng et. al. IEDM 2013.A. Khakifirooz et. al. EDL 2012.A. Khakifirooz et. al. VLSI 2012.Q. Liu et. al. IEDM 2014. Figure 1

(Invited) Variability and Performance on FDSOI Technology with Strained SSOI Substrate and SiGe Channel

Fully Depleted SOI (FDSOI) technology has been introduced at the 28nm node as a low-cost alternative strategy to FinFET. Developments on-going on 22nm and 14nm demonstrates the interest of this technology for CMOS scaling. In this talk, mismatch on FDSOI technology will be presented in order to list the main contributors of local variability. Back-bias impact on electrical parameters and variability will be discussed. Then, the effect of strain boosters on device variability and performance will be presented, including strained SOI substrates (sSOI), SiGe channel and compressive/tensile CESL layer.

Investigation of Coulomb scattering on sSi/Si0.5Ge0.5/sSOI quantum-well p-MOSFETs**Project supported by the National Natural Science Foundation of China (Nos. 61306126, 61306127, 61106015) and the CAS International Collaboration and Innovation Program on High Mobility Materials Engineering.

sSi/Si0.5Ge0.5/sSOI quantum-well (QW) p-MOSFETs with HfO2/TiN gate stack were fabricated and characterized. According to the low temperature experimental results, carrier mobility of the strained Si0.5Ge0.5 QW p-MOSFET was mainly governed by phonon scattering from 300 to 150 K and Coulomb scattering below 150 K, respectively. Coulomb scattering was intensified by the accumulated inversion charges in the Si cap layer of this Si/SiGe heterostructure, which led to a degradation of carrier mobility in the SiGe channel, especially at low temperature.

Prospects of High-Ge-Content Strained SiGe for Advanced FinFET Generations

High mobility materials such as strained Si1-xGexor III-V are promising channel candidates for advanced FinFET generations. By incorporation of moderate Ge content (x~0.2-0.3) into the channel of FinFETs, we have demonstrated pMOSFETs with superior extrinsic and intrinsic electrical characteristics suitable for 10nm technology generations and beyond [1]. To further boost pMOS FinFET performance, High-Ge-Content (HGC) SiGe FETs have recently drawn significant attention due to their enhanced transport and reliability properties and compatibility with bulk or SOI substrates [2, 3]. In addition, compared to strained pure germanium, they can offer reduced off-state tunneling leakage due to their relatively larger bandgap [4]. It has been observed that with high-Ge content around x~0.7, superior hole mobility values are achievable for planar biaxial strained SiGe on relaxed buffer layers and the mobility sensitivity to the strain level from underlying relaxed buffer is small when the buffer Ge content is above 30% [5]. Thus, HGC SiGe is an attractive pFET candidate especially when considered as a counterpart for nFET with s-Si FinFET technology [6], where higher Ge content is indeed required to compensate the built-in tension of s-Si. Utilization of HGC SiGe in a FinFET architecture by direct epitaxial growth is quite challenging due to very low (sub-10nm) epitaxial critical thickness constraints, resulting in high levels of defectivity which may be detrimental to the device functionality. In advanced FinFET technologies, relatively tall fins in tight pitches are required to increase the current per foot print and this may be quite challenging for high-Ge content strained SiGe FinFETs. Alternate approaches such as enhanced 3D Ge condensation [3] may be considered to mitigate the aforementioned issue. On the other hand, gate stack and interface passivation of SiGe with mid to high Ge range is more challenging than pure Si or pure Ge channel MOSFETs. While traditionally Si cap has been used to passivate the SiGe MOSFETs, this approach may not be optimal for scaled nodes where scaled EOT is required for electrostatics integrity of the transistors. Most devices fabricated using a Si-cap-free approach exhibit high levels of interface trap densities leading to mobility degradation and increased sub-threshold leakage. Moreover, enhance trap assisted tunneling can happen in the off state for high-Ge content SiGe due to its lower bandgap. In this talk, we review IBM's recent research activities on HGC SiGe FinFETs with Ge content over 50%. In particular, gate stack, passivation and EOT scaling are major factors in achieving high quality devices based on HGC SiGe. We present our results based on a Si-cap-free surface passivation combined with aggressive EOT scaling down to sub-7Å to achieve acceptable sub-threshold swings for both gate first and replacement high-K/metal gate FinFET integration flows. The width dependence of hole mobility for various device sizes from very wide (planar) to ultra-narrow (scaled FinFETs) would be presented and discussed in detail. In addition, various short channel device aspects such as impact of S/D junction process on performance and electrostatics, off-state leakage current, transconductance and current drive would be discussed. We conclude that high-Ge content SiGe FinFETs are suitable candidates for advanced high-performance logic FinFET applications, especially at low operating voltages (VDD), while their suitability for low or ultra-low power applications is questionable.

(Invited) Anisotropic Strain Introduction into Si/Ge Hetero Structures

Ge is one of the most attractive materials toward ultra-low-power and high-performance complementary metal oxide semiconductor (CMOS) circuits owing to its higher hole mobility than Si and various III-V materials. Moreover, it is possible to enhance the mobility further by introducing strain into the channel. Especially an uniaxial strain is expected to provide the highest hole mobility [1,2]. So far, several approaches have been researched to create uniaxially strained SiGe and Ge channels. We have been developing the selective ion implantation technique to induce uniaxial strain into SiGe buffer layers [3,4]. In this method, a Si substrate is selectively subjected to the ion implantation and followed by the SiGe overgrowth. A subsequent post-growth-annealing promotes the strain relaxation of the SiGe selectively in the implanted region as the implantation-induced defects formed act as dislocation nucleation sources. And hence, with proper configurations of the selective implantation, the anisotropic strain can be induced in the SiGe in the unimplanted area since the neighboring relaxed SiGe films in the ion-implanted areas provide shear stress at the interfaces. In previous works, we succeeded in fabrication of uniaxially strained SiGe buffer layers with Ge concentrations below 30% [3,4], which can serve as proper templates for uniaxially strained Si/Ge heterostructures, such as uniaxially strained Si and Si1-xGex (x < 0.5) channels. For the formation of uniaxially strained Ge and Si1-xGex(x > 0.5) channels, however, SiGe buffers with higher Ge concentrations are required. In this study, therefore, we fabricate uniaxially strained SiGe buffer layers with high Ge concentrations with the selective ion implantation technique and overgrew uniaxially strained Ge layers on the SiGe buffers. The sample fabrication procedure is as follows (Fig.1). Ar+ ions were selectively implanted into the Ge substrate through the SiO2 mask window. Line widths of the ion-implanted and unimplanted regions were varied from 2 to 20 μm. A SiGe layer was pseudomorphically grown on the selectively ion-implanted Ge substrate with solid source molecular beam epitaxy. Subsequently, postgrowth annealing was carried out to promote the strain relaxation of the SiGe only in the implanted region. Finally a Ge layer with the thickness of 10 nm was pseudomorphically grown on the SiGe. Figure 2 shows a Raman mapping image for the sample with 3-μm-width stripe lines, where a Ge-Ge mode peak wavenumbers obtained from the top Ge layer were scanned. A clear contrast is observed corresponding to the large and small compressive strain of the Ge layer in the implanted and unimplanted regions, respectively. This demonstrates that the strain of the Ge is laterally controlled by the selective implantation. Since XRD measurements confirmed that the SiGe buffer layer has uniaxial strain, it can be said that the top Ge layer is also uniaxially strained. This uniaxially strained Ge layer can be transferred onto the insulator substrate via wafer bonding process, where the ion-implanted defective region can be removed. Finally defect-free uniaxially strained GOI substrate can be obtained, which is applicable to high mobility uniaxilly strained Ge channel MOSFETs. [1] Y. Sun, et al., J. Appl. Phys. 101, 104503 (2007). [2] T. Krishnamohan et al., IEDM Tech. Dig., 899 (2008). [3] K. Sawano et al., Appl.Phys.Express 1, 121401 (2008). [4] K. Sawano et al., J. of Crystal Growth 378, 251 (2013). Figure 1

(Invited) Group IV Epitaxy Applications for Enabling Advanced Device Scaling

In the past decade, the surge of demand for mobile devices has been tremendous, and has been a key growth engine for the semiconductor market. These novel devices have all capabilities for sophisticated mobile communication, as well as capabilities for gaming, computing, etc. To address the stringent requirements in terms of battery lifetime, device speed, and scaling, the design and manufacturing processes of mobile devices needs constant innovation. Historically, Group IV epitaxial processes such as e-SiGe source/drain have played a critical role in meeting the needs for device scaling and performance in planar devices. One dramatic change that has taken place to address device scalability is the move to the multigate architecture of the FinFET (Fin Field Effect Transistor), which enables the virtual increase of the gate length and dramatically improved electrostatic performance. Beyond FinFET, the GAA (Gate All around Transistors) device structure is one of the most promising paths for offering another disruptive leap in device scaling. This paper discusses the increasingly critical role of epitaxy applications for enabling both of these new device architectures, which have much more complex integration schemes and tighter process control requirements than planar devices. We first review the overall trends for advanced CMOS devices in terms of scalability and performance. To carry on Moore’s law, devices need to be scaled from node to node. To enable this scaling, taller, more rectangular FinFETs with narrower body width at scaled pitches has been demonstrated. However this leads to several key process and integration challenges such as Fin integrity, capacitance increase, Channel mobility, sub-fin isolation, sidewall doping as well as contact resistance reduction. Next, we review the challenges of increasing FinFET device performance (e.g., mobility boost) by using SiGe p-channel FinFET, which has gained quite a lot of attention in the past several years. Several SiGe integration approaches have been reported in the literature, all which are enabled by new epitaxy applications. Examples of these SiGe channel integration approaches include SiGe replacement channel, STI last SiGe formation, cladded SiGe and SiGe condensation. There are significant integration challenges for each of these approaches from the perspective of epitaxial growth and related processes. For example, each of SiGe channel formation schemes have some specific requirements not only on the pre-clean and/or epi growth but also on the overall CMOS integration scheme (alleviation of SiGe oxidation, recess, Fin shaping, junction formation etc.). Consideration of the entire process flow is critical to ensure maximum strain is achieved in the channel with very low defectivity – two critical requirements for High Volume Manufacturing of high performance, low power devices. These topics will be explored in detail for several of the integration approaches mentioned above. Finally, we will discuss the potentially disruptive transition to a new device architecture – the Gate-All-Around (GAA) transistor - and discuss new epitaxy opportunities, requirements and challenges for this new device type.

Improvement of Boron Doping in SiGe Raised Sources and Drains for FD-SOI Technology by Carbon Incorporation

In semiconductor industry, the continuous scaling reduction of CMOS components improves devices performances and reduces manufacturing cost. However, the electrostatic control of the channel must be very accurate. To address this requirement, Fully-Depleted Silicon-On-Insulator (FD-SOI) technology, relying on the use of ultra-thin SOI films (less than 10 nm), is a promising option for the technical nodes beyond 14nm. This option requires the realization of Raised Source & Drain (RSD) by epitaxial Chemical-Vapor Deposition (CVD) of silicon alloys [1, 2]. The quality of the RSD epitaxy depends on the cleanliness of the surface before the deposition. For standard SOI technology, the state of the art generally consists in a high temperature treatment of the surface (>1000°C) in presence of hydrogen. However, such a thermal budget cannot be used for ultra-thin SOI films that dewets and agglomerates into 3D islands in this temperature range [3, 4]. Therefore, for ultra-thin SOI films, an efficient low temperature surface preparation process is required to avoid improper growth of Si or SiGe:B ( resp. SiC:P) layers, used as RSD material for pFET (resp. nFET). This works focus on the surface preparation prior to the low-temperature epitaxy of Si0.7Ge0.3:B layers on full-sheet and patterned wafers. In a first stage different processes of surface preparations are evaluated including standard wet cleans (HF-last, HF-RCA), plasma-based clean (SiCoNiTM setup [5, 6]) and their combination. For SiGe channels, the so-called HFRCA + SiCoNi process without any subsequent baking is recommended to reach clean surfaces [7]. In a second stage, we show that the Si1-xGex growth rate increases linearly when increasing the B2H6 boron-precursor gas flow. However the quality of the SiGe:B epitaxial films is degraded for high boron doping (≈1021at.cm-3) with B accumulation at the interface (Fig. 1). We report on the conditions necessary to reach high boron concentrations while maintaining a uniform boron concentration by incorporating carbon (≈1%) in the RSD deposition step. A wide set of characterization tools are used to assess the sample quality in terms of defect density, chemical analysis, roughness and surface morphology: AFM, SEM, TEM, Spectrometric Ellipsometry (SE), EDX, XPS, Secondary Ion Mass Spectroscopy (SIMS), Model Based Infrared Reflectometry (MBIR), Atom Probe Tomography (APT), Spectroscopy Infrared Reflectometry (SIR) and Low-Energy Electron Microscopy (LEEM). Keywords: Si, SiGe, SiCoNiTM Preclean, FD-SOI, SiGe:B, WET clean, RSD

Thermal Rounding Kinetics and Demonstration of Steep and Flat Facets Succession in Selective Si-Based Epitaxy

Si1-xGex(SiGe) alloys are integrated in more and more complex structures, and their applications are numerous. Initially, epitaxy process was applied for SiGe channels in 32nm technologies and beyond [1]. In the 20nm technology generation, SiGe epitaxial growths are used for raised source/drain (RSD) in Fully Depleted Silicon-On-Insulator (FD-SOI) p-Metal Oxide Semiconductors (p-MOS). However, since the scaling of the transistors’ dimensions is reaching physical, material, and technological limitations [2], new challenges in Si-based technologies have to be defined. Up to now, one of the most promising studies overcoming major device issues such as parasitic capacitance [3], is the morphology’s control of SiGe epitaxial growths. This is the reason why the morphological behavior of epitaxial SiGe is of great interest for performance improvements. In SiGe epitaxies, surface morphology depends on different parameters such as deposited thickness, Ge content... But, one of the most important parameters for the morphological change is the thermal budget brought to the film during or after epitaxial growth. The consequence of a thermal budget on an epitaxial layer is the modification of the morphology to reduce the surface energy leading to thermal rounding. Finally, the transistors’ dimensions being very small, the morphology is even more affected and sensitive to any process conditions (temperature, pressure), and extensive studies on SiGe morphology are needed. For this work, patterned 300mm Si(001) bulk wafers are used as substrates. All the layers were selectively grown in a Rapid Thermal Chemical Vapor Deposition reactor using dichlorosilane, germane, and HCl chemistry at low pressure and relatively low temperature. The purge and unloading steps were adjusted to freeze the as-deposited morphology. This way, the observed morphology is the closest as possible to the one during the deposition. The first part consists of a quantitative study of the thermal rounding’s kinetics in Si1-xGex (x=0.25) epitaxies. To do so, as-deposited SiGe layers are annealed at different thermal budgets. Then, the morphology evolution during annealing is studied as a function of temperature and time. The results of post annealed SiGe epitaxies are reported in Fig.1. It is observed that an annealing temperature increase of 25°C (from 650°C to 725°C) considerably impacts the morphology which evolves progressively passing through different steps. First, the edges begin to round and retract. In this step, the as-grown facets and their corresponding overgrowths fade away completely. Then, the thermal rounding gives rise to a formation of rounded ridges all around the pattern. Finally, the corner ridges approach towards each other until they collapse to form a single large dome. The rounding kinetics is quantified by measuring the displaced volume of matter. In the final paper, an extensive study will be given in which the effect of H2pressure on the kinetics will be presented. It will be shown that the pressure has a real influence on the rounding effect due to an increase of the hydrogen coverage slowing the Si diffusion at the surface. In many MOS applications, the SiGe epitaxy has to be capped typically with a Si (or SiGe) layer to maintain good performances. In this second part, the morphology behavior of such caps is studied. Si and SiGe layers of different thicknesses, growth rates and Ge contents were grown on a rounded SiGe layer, prepared as explained in the first part. It is shown that both Si and SiGe behave differently. The SiGe cap decreases the surface undulation amplitudes more efficiently than Si. Indeed, in large patterns, the 16 nm thick SiGe cap surface is smoother (RRMS=3.57nm) than the surface of Si cap (RRMS=7.37nm) (see Fig.2). In small patterns, a regular faceted morphology is observed for thick SiGe cap which is not the case for Si cap, showing once again that SiGe cap is more efficient (Fig.3). On the other hand, for thin Si and SiGe caps, the top surface presents domes with a succession of flat and steep facets. Those facets are <113> facets for the steep ones, and <11h> with h being 9 or even more, for flat facets (Fig.4). To summarize, firstly, the thermal rounding has been quantified and shown to be very sensitive to moderate thermal budgets (e.g.700°C). Secondly, Si and SiGe caps deposited on such a rounded surface have been compared. It has been reported that thin caps present successive terraces rather than regular faceted morphology. Keywords: SiGe, Si, Epitaxy, Rounding, Capping. [1] Weber,O Symp. VLSI Techno Dig Tech Pap, 2004, p. 42. [2] Haron,N. IEEE, 2008; pp 98–103. [3] Cheng,K. Symp. VLSI Tech., 2009, pp 212-213. Figure 1

(Invited) A Brief History of Selective Epitaxy (at IBM SRDC)

Over more than a decade—and half a dozen technology nodes—selective expitaxy has consistently been a major performance element, propelling logic devices to their ultimate targets. Throughout this period (the “Epi Renaissance”), a huge variety of epitaxial processes have been evaluated across the semiconductor industry. Because each technology generation has unique constraints and process assumptions, these epitaxy processes have varied significantly in shape, size, and composition. And of course not all survived to be implemented in full production. This presentation gives a retrospective survey of each of these epitaxial processes, ranging from a simple, single undoped Si raised source/drain to multi-pass growth with complex multi-layer film stack. Selective epitaxy at IBM SRDC began with an undoped selective Si raised source drain (RSD) at the 90nm technology node, used to improve the silicide formation and placement. This was a key enabling feature of the Si on SiGe on insulator (SGOI) technology [1]. Since the silicide had difficulties with the SiGe underlayer, a selective epitaxial Si solution allowed significantly improved contact resistance. SGOI showed great promise on long channel devices, and due to the uniaxial nature of the strain it showed a clear performance benefit on both NFET and PFET. Unfortunately, the short channel devices were consistently degraded, so for the ultimate performance targets IBM instead turned to stressed nitride liners to deliver channel strain [2], while Intel introduced embedded SiGe source/drain (eSiGe) [3]. IBM incorporated eSiGe as a PFET performance element starting at the 65 nm node. However, instead of an in-situ boron doped eSiGe grown just prior to silicide (late eSiGe) similar to what Intel had published, IBM used a lower %Ge, undoped SiGe film grown just after gate module (early eSiGe). Early eSiGe was effectively a “drop-in” solution that allowed for minimal disruption to the existing integration and device design while still providing significant performance gains via channel strain [4]. For the 45nm node IBM published a novel method called Hybrid Orientation Substrate (HOT) that enabled PFET performance gain by changing the PFET Si crystal orientation from <100> to <110>. This method utilized a SOI wafer with <100> top Si layer bonded to a <110> handle wafer. At the beginning of the process, the PFET regions were etched down through the buried oxide, and a thick, undoped selective Si epi was then re-grown on the <110> substrate. In contrast to SGOI the benefit of HOT was demonstrated even on short channel devices. Even better, this mobility increase was shown to be additive with eSiGe strain [5]. Unfortunately a combination of factors including significantly higher substrate cost, area density penalty from expanded groundrules, and concerns about defectivity of the selective epitaxial re-growth prevented it from being implemented in full manufacturing. Instead of HOT, a second generation early eSiGe process was developed with closer proximity to the gate, and increased recess depth [6]. At the 32nm node IBM was focused on the switch to high-K with metal gate, and again IBM and Intel’s solutions diverged. IBM and partner companies used a “gate first” integration flow, contrasted with Intel’s “gate last” replacement metal gate process. Since differential metal workfunction tuning was unavailable in the gate-first integration, IBM introduced a second epitaxy step, growing a thin layer of channel SiGe on the PFET in order to separately tune the PFET threshold voltage [7], and increase performance [8]. Despite remaining planar and gate first, 22nm saw multiple disruptive changes in the source/drain epi module. IBM gained an industry first with the introduction of strained Si:CP in the NFET S/D, a process that required cyclic dep/etch in order to achieve high substitutional carbon incorporation [9]. On the PFET side, the reduced dimensions and the effect of ion implant lateral straggle finally forced a switch from early to late eSiGe. This change drove increased complexity in the epi by adding a buffer layer to control dopant out-diffusion, a ramped high-boron main layer, and a cap layer for improved silicide. Additionally, both NFET and PFET benefited from the introduction of an integrated preclean module, where the wafer does not break vacuum in between oxide etch and epitaxial growth. Today, the 14nm node marks the arrival of FinFETs at the SRDC – with significant integration differences compared to Intel’s FinFET solution. IBM chose to stay with SOI substrate, leading to challenges with the source/drain recess for embedded SiGe. Eventually, IBM sidestepped the recess issue by implementing cladded epitaxy for both the PFET and NFET source/drain, focusing on improving performance by lowering contact resistance instead of straining the channel [10]. Figure 1

The effect of CESL and dummy poly gate for n-type MOSFETs with short Si0.75Ge0.25 channel

In this investigation, the n-channel metal–oxide–semiconductor file–effect transistor (MOSFET) with contact–etch–stop–layer (CESL) stressor, SiGe channel, and dummy poly gate is proposed. The simulated technique is utilized to explore the stress distribution of nMOSFET with the channel region induced by foregoing mechanical. We use ANSYS software, which is based on finite element analysis (FEA), to simulate the stress distribution in the channel region. The simulation results indicated the CESL and SiGe channel significantly affected the stress distribution within the channel region. The sources of loading are 1.1, 2, and 3 GPa tensile CESL (t-CESL) and a SiGe channel structure with 25% germanium (Ge) mole fraction. The effect of dummy poly gate is discussed, including the dummy poly gate number and various pitches of the dummy poly gate. The simulation results indicate that the pitch of the dummy poly gate substantially influences the number of dummy poly gates. The electron mobility enhancement in the inversion layer of n-channel MOSFET was discussed. Electron mobility enhancement was evaluated by piezoresistance coefficients. Hence, the percentages of improvement of electron mobility with different structural conditions were compared. The relationships between stress distribution in the channel and dummy poly gate layout could be understood clearly through systematic analysis.

(Invited) UTBB FDSOI PMOSFETs Including Strained SiGe Channels at the 14nm Technology Node and Beyond

We have physically and electrically characterized pMOSFETs of compressively strained SiGe channel built on Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI). Such a channel greatly contributes to the FDSOI CMOS high-performance at the 14nm node. At the same time, it induces strong layout effects, which are reported and explained in this paper. They can be reproduced by an accurate physics-based electrical model, which enables us to predict the device and design performance for various technological configurations: germanium concentration in the channel, isolation and channel process integration. In order to mitigate the impacts of the SiGe channel relaxation, we have studied two kinds of solutions. First, technological solutions are possible, leading experimentally to a -15 percent delay reduction for a ring-oscillator of 1-gate finger inverters at 0.8V supply voltage. Secondly, we demonstrate the benefits induced by smart design layouts, enabled by process integration goodies and some layout constructs. Namely, a continuous-RX design, which consists in a long active line configuration, optimizes the stress configuration, maintaining a high level of longitudinal compressive stress, while relaxing the transverse one. A 28 percent ring oscillator delay improvement is experimentally demonstrated at a given leakage for 1-finger inverter at 0.8V supply voltage. This demonstrates the interest of process/design co-optimization of strain-induced layout effects. Finally, we discuss the technological knobs and especially the strain boosters that can furthers the scaling of FDSOI below the 14nm node: SiGe channel and source/drain of high-Ge content, influence of the surface orientation and channel direction, as well as the gate last integration.

(Invited) Variability and Performance on FDSOI Technology with Strained SSOI Substrate and SiGe Channel

Fully Depleted SOI (FDSOI) technology has been introduced at the 28nm node as a low-cost alternative strategy to FinFET. Developments on-going on 22nm and 14nm demonstrates the interest of this technology for CMOS scaling. In this talk, mismatch on FDSOI technology will be presented in order to list the main contributors of local variability. Back-bias impact on electrical parameters and variability will be discussed. Then, the effect of strain boosters on device variability and performance will be presented, including strained SOI substrates (sSOI), SiGe S/D and compressive/tensile CESL layer.

(Invited) Germanium Enrichment for Planar-, Fin- and Nanowire-Channel MOSFETs Made on SOI

This paper discusses the fabrication of SiGe channel for Ultra-Thin Body and Buried oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) MOSFETs, FinFETs and Nano Wire FETs (NWFETs). Enrichment conditions need to be tuned to avoid excessive Ge pile-up on tensile-strained planar Si films due to lower Ge diffusion. Patterning SiGe Fins in thick blanket SiGe layers faces the crystal quality limits set by plastic relaxation beyond critical thickness. As an alternative, Ge enrichment of pre-existing Si Fins requires conformal SiGe growth and can produce strained SiGe Fins up to 50% without significant relaxation, independently from Fin height. Enrichment requirements for NWFETs are identical to those of planar devices. As a result, NWFETs benefit from both SiGe mechanical stability and uniaxial compressive strain performance enhancement.

Effects of High-k Dielectric Materials on Electrical Characteristics of DG n-FinFETs

nanoscale n-channel double gate fin field-effect transistor (FinFET) structures and their sensitivity to gate dielectric materials with different channel materials using SiGe and 3CSiC in the channel region. In this work, the numerical tool Atlas Silvaco was used to simulate the device in three dimensions and evaluate the electrical characteristics of the device at 300K. The influence of the gate dielectrics on threshold voltage roll-off, subthreshold slope, transconductance, drain induced barrier lowering, leakage current, on-current, and on/off current ratio has been investigated. The simulation results show that high drain current and transconductance were obtained with SiGe channel material. The results also show that a higher value of gate dielectric constant can increase the drain current and improve the leakage current. Drain induced barrier lowering is reduced with the increase in gate dielectric constant. It can be noticed with different and useful results which led researchers to further manufacturing process in order to get the complete device.

Low Thermal Budget Microwave Annealing for Nisige Schottky Junction Device

I. Background/ Objectives and Goals As continuously scaling down the devices for logic circuit, higher mobility channel materials have been considered to boost driving current such as Ge or SiGe. However, most high mobility materials have a significantly smaller bandgap as compared to Si, which will result in higher Band-To-Band-Tunneling leakage. As a result, S/D and channel engineering must play leading role for boosting the device performance. We, therefore, propose a NiSiGe/n-Si Schottky Junction formed microwave-annealing for the Si capped SiGe quantum well devices (Si/SixGe1-x/Si,x=0~1). II. Methods Fig. 1 shows Process flow of fabricating NiSiGe/n-Si Schottky diodes. The multi-layer structure of Si/Si0.57Ge0.43/Si was grown by ultra-high vacuum chemical vapor deposition system. The channel composed of a 5nm-thick SiGe with biaxial compressive strain and Si cap was grown at 420~500 and 550 °C, respectively. Isolation film SiO2 was deposited on multi-layer architecture after series surface cleaning. Then, the definition of junction active area was accomplished with lithography and wet-etching. Because of bulk annealing characteristic of microwave, the technique was utilized to form NiSiGe as low leakage Schottky junction ranging from 370 to 470 °C for 150 s in N2 ambient. The un-reacted Ni film was removed, followed by Al deposition as the back contact. The characteristics of microwave-annealed-NiSiGe Schottky junction was investigated with AFM, SEM, TEM, XRD, and electrical analyzer. III. Expected Results The SEM images demonstrated the surface morphologies of NiSiGe layer with various annealing temperatures in Fig.2 NiSiGe agglomeration emerged as forming temperature up to 600 °C by rapid thermal annealing (RTA) which will lead to unstable junction current. Relatively, microwave annealing can suppress the formation of junction defects and prevent the agglomeration due to lower forming temperature. For the purpose of distinguishing the pros and cons between the rapid thermal annealing (RTA) in Fig.3(a) and microwave annealing in Fig.3 (b), I-V characteristics were evaluated to check the electrical performance of Schottky junction. Microwave-annealed Schottky junction exhibited better ION/IOFF ratio about 3×105 formed at 390 °C and more stable off-current characteristic as compared to the one with rapid thermal annealing (RTA). In addition, barrier height and ideality factor of the microwave-annealed Schottky was 0.62 eV and 1.07, respectively. High resolution TEM images showed the polycrystalline structure, good uniformity of the NiSiGe and a distinct interface between NiSiGe and Si in Fig.4. IV. Conclusion Microwave annealing is beneficial in integrating quantum well p-channel MOSFETs with Schottky S/D because of its low temperature feature. We believe our microwave-cooperated quantum well architecture is promising for the high performance logic circuits and enable SiGe or Ge channel devices to be integrated on the Si substrate for the future applications. V. R eferences [1] M. S. Datta, G. Dewey, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, R. Kotlyar, M. Metz, N. Zelick, and R. Chau, “High Mobility Si/SiGe Strained Channel MOS Transistors with HfO2/TiN Gate Stack,” IEEE International Electron Devices Meeting, p.28, Dec. 2003. Figure 1