Abstract
This paper discusses recent progress in and challenges of threshold voltage control for advanced high- k/metal-gated (HKMG) devices. It presents the impact on threshold voltage ( V t) control of incorporating La and Al into HKMG devices. A dipole moment model explaining V t tuning of HfSiON/metal-gated MOSFETs is proposed. In addition, a dual channel scheme that allows La 2O 3 capping in NMOS and a SiGe channel in PMOS to achieve acceptable V t for HKMG CMOS devices will be discussed. Also shown is the impact of the robustness of the SiO 2/Si interface on the HKMG MOSFET V t-equivalent oxide thickness (EOT) roll-off. Finally, techniques to improve the interface quality of a HKMG stack will be discussed.
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