Improvement in threshold voltage control by minimizing boron penetration in a LV-GCMOS technology

Abstract

Maintaining tight threshold voltage (V/sub T/) control for a low-voltage CMOS process is critical due to the large impact of V/sub T/ on circuit performance at low power supply voltages. In this paper, PMOS V/sub T/ was shown to be sensitive to poly gate thickness and BF/sub 2//sup +/ source/drain implant energy. This data helped identify boron penetration as a prime contributor to PMOS threshold voltage variation. SIMS measurements were used to investigate boron diffusion through the poly gate at various stages in the process flow. These SIMS profiles pointed to the low-temperature thermal cycle of the nitride spacer deposition as a key step which influenced the amount of boron penetration and thus the final device threshold voltage. Experimental evidence shows that the temperature gradient across the nitride spacer deposition furnace causes a variable amount of boron penetration resulting in a large variation in PMOS V/sub T/. We adopted a process flow change which virtually eliminated boron penetration and significantly reduced the sensitivity of the devices to manufacturing variations. Threshold voltage variation was reduced by a factor of two.