Si-implanted GaAs Research Articles

Phosphorous coimplantation effect on threshold voltage uniformity of GaAs transistors

Phosphorous coimplantation effect on electrical uniformity of Si-implanted GaAs active layer is investigated for undoped as-grown, undoped ingot-annealed, and In-doped substrates. Pairs of field-effect transistors, fabricated with and without P coimplantation, are placed on whole 3-in.-diam substrates at a 200-μm interval. Threshold voltage measurements reveal that a concentration of 1018 /cm3 coimplanted P reduces the standard deviation in threshold voltage for undoped as-grown substrates to 1/2.5. Undoped ingot-annealed substrates achieve the same uniformity of threshold voltage as In-doped substrates, which showed the best data. Moreover, this method reduces the variation in the mean threshold voltage among substrates by one-half. These results indicate that P coimplantation successfully suppresses the change of As to Ga vacancy concentration ratio.

The effect of the pattern shape of Hall devices in the electrical characterization of Si-implanted GaAs

We show that the Greek-cross pattern effectively reduces the error due to finite-sized contact in Hall-effect measurements. This pattern enables measurements of areas as small as 4×4 μm, which is comparable to the n-channel area of GaAs field-effect transistors. We find that the sheet carrier concentration agrees well with the value derived from the capacitance-voltage method using this pattern. This indicates that the small Greek-cross pattern is suitable for electrical property characterization of active layers.

Rapid thermal annealing of GaAs in a graphite susceptor—comparison with proximity annealing

Rapid thermal annealing of GaAs within an enclosed, SiC-coated graphite susceptor is shown to eliminate slip formation during implant activation treatments (900 °C, 10 s) and to provide much better protection against surface degradation at the edges of wafers compared to the more conventional proximity method. The peak carrier concentration obtained in Si-implanted (3×1012 cm−2, 60 keV) GaAs by both methods is comparable, but the wafers annealed in the susceptor have tighter carrier profile width distributions measured over the whole wafer area.

Correlation of Void Formation with the Reduction of Carrier Activation and Anomalous Dopant Diffusion in Si-Implanted GaAs

AbstractWe report the study of high-dose Si-implanted GaAs containing doses ranging from 1×1014 to 1×1015 cm-2 and with subsequent anneals at 850°C for 1 hour. At doses ≥ 3×1014 cm-2, a severe reduction of carrier concentration and anomalous Si diffusion are observed in the near-surface region. In the same region, small, near-spherical voids are found by transmission electron microscopy. In contrast, for samples implanted with doses ≤ 1×1014 cm-2, voids are not found, and both normal carrier activation and Si diffusion profiles are observed. The concurrent onset of these three phenomena in the same region in high-dose samples leads us to conclude that the severe reduction of carrier concentration and anomalous Si diffusion are attributable to the formation of voids.

Dislocation effect on the activation efficiency profile in Si-implanted and SiN-capped annealed GaAs

Depth profiles of carrier concentration and photoluminescence (PL) intensities are measured for Si-implanted and SiN-capped annealed GaAs. The peak carrier concentration decreases far from dislocations without a change in the effective thickness of the active layer. Moreover, the activation efficiency of the implanted Si decreases and the PL intensity of the Si on the arsenic site (SiAs) acceptor increases in the surface region of the active layer. These results suggest that the As vacancy concentration increases during the annealing process, and this enhances the effect of dislocations which creates an electrical nonuniformity of the Si-implanted GaAs layer.

Electron-beam evaporated phosphosilicate glass encapsulant for post-implant annealing of GaAs

Electron-beam deposited films of phosphosilicate (PSG) have been investigated as dielectrics for the encapsulation of Si-implanted GaAs for the purpose of post-implant annealing. The processing parameters that were optimized included the thickness of PSG film, the substrate temperature, and the annealing time and temperature. PSG films deposited at temperatures ≥300 °C showed no signs of deterioration up to temperatures in excess of 900 °C for 30-min anneals carried out in a forming gas and/or nitrogen ambient. Depth profiles in excellent agreement with the Lindhard–Scharff–Schiott curves were obtained with 1000-Å-thick films when annealed at 850 °C for 30 min. The diffusion coefficient of implanted silicon was found to be an order of magnitude smaller for the PSG films than that for the conventional plasma assisted chemical vapor deposited SiO2 films at 850 °C.

Lattice imaging study of in-depth disordering of Si-implanted GaAs

Cross-sectional high resolution transmission electron microscopy has been used to obtain direct information on the in-depth radiation damage distribution of weakly damaged GaAs by Si-ion implantation. A comparison is made between the experimental data and the calculated (using TRIM computer simulations) deposited energy by nuclear stopping for the same conditions. In particular a diffusion zone, with 200–300 A width, of high point defect concentration beyond the damage peak is detected. These point defects are interpreted as As interstitials. By direct observation, information concerning the damage- and radiation-enhanced diffusion in implanted III–V compound semiconductors is obtained.

Damage assessment in low-dose Si-implanted GaAs by Raman spectroscopy

Allowed and forbidden first-order as well as resonant second-order Raman scattering has been used to study implantation damage in low-dose (5×1011–1×1013 cm−2) 29Si+-implanted GaAs. Symmetry forbidden scattering by longitudinal optical (LO) phonons and allowed 2LO scattering were found to be most sensitive to lattice damage for the range of implantation doses given above. The intensity ratio of the 2LO peak to the forbidden LO phonon line measures variations in the implantation dose with an accuracy better than ±7% for an average dose of 2×1012 cm−2. The potential of spatially resolved Raman spectroscopy for the assessment of homogeneity in as-implanted GaAs wafers has been demonstrated.

Experimental study on the correlation between thermal-wave signals and dopant profiles for silicon-implanted GaAs

The correlation between the contour maps of thermal-wave signals and those of carrier concentrations in GaAs substrates was investigated to understand which portion of an implanted profile mainly corresponds to the generation of thermal-wave signals. It was found that the thermal-wave signals on a Si-implanted GaAs wafer showed good correlation with the peak concentration in the carrier profile obtained from capacitance-voltage (C-V) measurements. This method is useful for the threshold voltage monitoring of GaAs metal-semiconductor field-effect transistors with a thin implanted channel layer, which cannot be characterized by conventional C-V measurement.

Characteristics of Si-Implanted (211) Versus (100) GaAs

ABSTRACTTransport, Raman and XPS measurements were made on SI-implanted (1.7×1013cm−2, 50keV) and rapid-thermal annealed (100) and (211) GaAs substrates In an effort to distinguish differences between the two orientations. With these techniques, no significant differences were found. The implant-damage depth was about 1200Å for both orientations, with slightly higher near-surface damage (and lower mobility) apparent for (211). No unusual features in the (211) carrier concentration profile, as was previously reported, were evident.

Damage Removal and Activation in Rapid-Thermally-Annealed Silicon Implanted Semi-Insulating GaAs

ABSTRACTIn the Rapid-Thermal-Annealing of Si-implanted undoped semi-insulating GaAs three regimes are broadly identified. At ˜ 600°C, ion implantation damage is largely removed, as indicated by lattice-strain measurements performed by X-ray rocking curves. Between ˜ 600 – 900°C, “extended defects”, which presumably account for the long tails in the electron concentration depth profiles, are annealed. Higher annealing temperatures in this range result in profiles with successively shorter tails. Finally, beyond ˜ 900°C, “acceptor levels” in the material are revealed, which become effective in compensating the Si activation.

Excimer and dye laser annealing of silicon-nitride-capped, Si-implanted GaAs

Carrier concentrations exceeding 1019/cm3 in GaAs implanted with Si (2×1014/cm2 at 140 keV) have been obtained by pulsed laser annealing with either a dye laser (λ=728 nm) or a XeCl excimer laser (λ=308 nm). Dye-laser annealing through a ∼55-nm-thick Si3N4 cap consistently produced higher activations than excimer-laser annealing with or without the cap. Carrier densities were measured by phonon-Raman and plasmon-Raman scattering.

Effect of As overpressure during annealing on the nonuniformity of activation efficiency in Si-implanted GaAs layer

The effects of As overpressure during annealing on nonuniformity, i.e., the variations of sheet carrier concentration and Hall mobility across wafers, have been studied for Si-implanted undoped semi-insulating GaAs. The nonuniformity was found to be suppressed by annealing under high As overpressure. It is suggested that the high As overpressure suppresses the As vacancy generation during annealing which may induce the nonuniformity due to the local variation of compensation ratio of [SiAs]/[SiGa] around a dislocation.

Damage induced by CHF3+C2F6 plasma etching on Si-implanted GaAs(100)

The damage induced by CHF3+C2F6 plasma etching on GaAs(100) was studied. We exposed GaAs(100) surfaces to various etching conditions and monitored sheet resistance, carrier concentration, and Hall mobility. Significant losses of Hall mobility and carrier concentration, and an increase in sheet resistance were observed only when CHF3 was introduced into the plasma. After annealing at 400 °C for 55 min, sheet resistance was restored nearly to the value obtained before the plasma exposure. We believe that the damage was produced by hydrogen atoms or ions dissociated from CHF3 in the plasma. In contrast to the general belief that plasma etching induces the least damage among dry etching techniques [such as reactive ion etching (RIE) and reactive ion beam etching (RIBE)], our plasma etching damage was comparable to previously reported RIE or RIBE damage.

Successive tem observation of defects in Si-implanted GaAs

A novel technique for preparing specimens for successive plan-view TEM observations of defects at various depths is developed. It is found with this technique that in Si +-implanted GaAs defect-bands are composed with dislocation tangles, pinnings, stacking faults and dislocation loops.

Activation efficiency improvement in Si-implanted GaAs by P co-implantation

Co-implantation effects of N, P, and As are studied for Si-implanted GaAs by the Hall effect and photoluminescence measurements. The P co-implantation enhances and homogenizes the activation efficiency of the implanted Si, and decreases photoluminescence peak intensities of the SiAs and the GaAs acceptors. It also suppresses the variation of the Si activation efficiency among the crystal ingots by half. These results indicate that P co-implantation is a promising method for fabricating active layers of high-performance GaAs large scale integrated circuits.

Surface-depletion effect correction to nonuniform carrier distributions by Hall measurements

Significant errors in the determination of carrier profiles obtained by the Hall-effect method result if the depletion effect at a semiconductor surface is not taken into account. A practical procedure for correcting the apparent measured carrier profiles for this surface-depletion effect is described for nonuniformly doped semiconductors. This correction method is then applied to Si-implanted GaAs and the results are compared with those of capacitance-voltage measurements. The number of total trapped charges in free-surface states are estimated to be about 1×1012 cm−2.

Annealing behavior of implanted Si in semi-insulating GaAs in the presence of stress

A thermodynamic theory of the annealing behavior of Si impurities in GaAs is presented. It is predicted that the ratio of the number of Si impurities at the Ga sites to that at the As sites is sensitive to the stress under which annealing or doping is performed. The ratio is above and below unity under a compressive stress and tensile stress exceeding a critical value, respectively. Therefore, the Si impurities act predominantly as donors and acceptors under the respective stresses. The theory is supported by our experimental finding that the Si-implanted GaAs becomes of p type by annealing under a tensile stress.

Electrical properties of p-type layer in Si-implanted GaAs

physica status solidi (a)Volume 97, Issue 1 p. K83-K86 Short Note Electrical properties of p-type layer in Si-implanted GaAs S. Shigetomi, S. Shigetomi Department of Physics, Kurume University Search for more papers by this authorT. Matsumori, T. Matsumori Department of Electronics, Faculty of Engineering, Tokai University Search for more papers by this author S. Shigetomi, S. Shigetomi Department of Physics, Kurume University Search for more papers by this authorT. Matsumori, T. Matsumori Department of Electronics, Faculty of Engineering, Tokai University Search for more papers by this author First published: 16 September 1986 https://doi.org/10.1002/pssa.2210970151 Mii-machi, Kurume 830, Japan. Shibuya-ku, Tokyo 151, Japan. AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Volume97, Issue116 September 1986Pages K83-K86 RelatedInformation

Si film as an annealing cap for Si-implanted GaAs

A Si film formed by vacuum deposition as an annealing cap for a Si-implanted GaAs substrate has been studied. GaAs substrates implanted with 3×1013 Si ions/cm2 at 100 keV were furnace annealed with Si caps at temperatures between 750 and 900 °C for 15 min. The existence of Ga and/or As atoms in the Si cap film was not detected in the Rutherford backscattering spectra of the Si films after annealing. The differential Hall measurement showed that the carrier concentration profile distributed within the ion implanted region. The Si cap film has feasible characteristics for annealing of Si-implanted GaAs.