Short-channel MOSFETs Research Articles

High-Performance $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ -Channel MOSFETs With High-$\kappa$ Gate Dielectrics and $\alpha$-Si Passivation

Long and short buried-channel In0.7Ga0.3As MOSFETs with and without alpha-Si passivation are demonstrated. Devices with alpha-Si passivation show much higher transconductance and an effective peak mobility of 3810 cm2/ V middots. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 muA/mum at Vg - Vt = 1.6 V and peak transconductance of 715 muS/mum. In addition, the virtual source velocity extracted from the short-channel devices is 1.4-1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance In0.7Ga0.3 As-channel MOSFETs passivated by an alpha -Si layer are promising candidates for advanced post-Si CMOS applications.

A new two-dimensional analytical subthreshold behavior model for short-channel tri-material gate-stack SOI MOSFET’s

On the basis of the exact solution of the two-dimensional Poisson equation, a new analytical subthreshold behavior model consisting of the two-dimensional potential, threshold voltage, and subthreshold current for the short-channel tri-material gate-stack SOI MOSFET’s is developed. The model is verified by its good agreement with the numerical simulation of the device simulator MEDICI. The model not only offers physical insight into the device physics but also provides guidance for the basic design of the device.

UV nanoimprint lithography process optimization for electron device manufacturing on nanosized scale

Imprint specific process parameters like the residual layer thickness and the etch resistance of the UV polymers for the substrate etch process have to be optimized to introduce UV nanoimprint lithography (UV NIL) as a high-resolution, low-cost patterning technique for research and industry into electron device manufacturing. Additionally, UV NIL processes have to be compatible with conventional silicon (Si) semiconductor processing. Within this work, the minimization of the residual layer thickness by using a multi-drop ink-jet system, which was integrated into the imprint stepper NPS300 from S-E-T-(formerly SUSS MicroTec), in combination with a low viscous UV polymer from Asahi Glass Company is shown. The etch resistance of different UV polymers against the poly-Si etch process was increased by 50% with an appropriate post-exposure bake. A poly-Si dry etch process was used to pattern the gates of short channel MOSFETs. After optimizing the poly-Si etch, properly working short channel MOSFETs with a minimum gate length of about 90 nm were fabricated demonstrating successfully the compatibility of UV NIL with conventional Si semiconductor processing on nanosized scale.

A New Impact-Ionization Current Model Applicable to Both Bulk and SOI MOSFETs by Considering Self-Lattice-Heating

In existing impact-ionization current (J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> ) models for short-channel MOSFETs, various models for the characteristic ionization length (I) or the velocity-saturation region length (l <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) have been developed by using the polynomial-fitting method in order to model the bias dependence of the maximum electric field (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) in the channel. This paper proposes a bias-voltage- and gate-length-dependent effective maximum electric field (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m,eff</sub> ) based on energy-balance equation, aimed at obtaining an accurate expression of E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> to increase the accuracy of the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> model for deep submicrometer devices. This new method overcomes the complicated modeling of I, avoids the extraction of different fitting constants for different devices, and enables unique extraction of the impact-ionization coefficients (A and B) for different devices. This improved model demonstrates excellent agreements with the numerical data of nMOSFETs from a 90-nm-technology wafer file. Only one unique set of parameters is needed to fit the data from devices with different biases and lengths for the same technology node. Moreover, since the lattice temperature (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">l</sub> ) is built in the formulation of E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m,eff</sub> , a compact I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> model with self-lattice-heating is developed, which also accounts for the excess substrate current observed in the SOI devices due to carrier heating in the channel.

Capacitance modeling of short-channel double-gate MOSFETs

We present 2-D physics based modeling of short-channel double-gate MOSFETs of nanoscale dimensions. We have derived a precise, self-consistent framework model for the device electrostatics, the drain current, and the charge conserving capacitances, covering all regimes of device operation from subthreshold to strong inversion. The modeling has no adjustable parameters and implicitly incorporates scaling with device dimensions and material composition. The foundation of the 2-D modeling is an analytical description of the inter-electrode capacitive coupling between the four electrodes, based on conformal mapping techniques. The model is shown to be in excellent agreement with numerical simulations.

A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET

A simple analytical model for deriving the front and the back gate threshold voltages of a short-channel fully-depleted SOI MOSFET is presented. Taking into account the lateral variations of the front and the back surface potentials, we obtain two-dimensional potential distributions in the fully depleted silicon body, the front oxide layer, and the back oxide layer. From the obtained two- dimensional potential in the silicon body, the minimum values of both front and back surface potentials are derived and used to describe both front and back gate threshold voltages as closed-form expressions in terms of various device geometry parameters and applied bias voltages. Obtained results are found to be in good agreement with the numerically simulated results.

Combining a Novel Charge-Based Capacitance Measurement (CBCM) Technique and Split $C$–$V$ Method to Specifically Characterize the STI Stress Effect Along the Width Direction of MOSFET Devices

The shallow trench isolation (STI) stress effect along the length direction on short-channel MOSFET devices has already been widely studied. However, the effect along the width direction has seldom been specifically analyzed. In this paper, we combine a novel charge-based capacitance measurement technique, which is used to extract the intrinsic of MOSFET devices, and the split capacitance-voltage method to extract the mobility of devices with various channel widths. Although it is already known that under the influence of compressive STI stress along the width direction the mobility of both NMOS and PMOS devices will degrade with decreasing width, it is the first time to quantify the impact of this STI stress component on MOSFET devices.

Characterization of ultrathin SOI film and application to short channel MOSFETs

In this study, a very dilute solution(NH4OH:H2O2:H2O 1:8:64 mixture) was employed to reduce the thickness of commerciallyavailable SOI wafers down to 3 nm. The etch rate is precisely controlled at0.11 Å s−1 based on the self-limited etching speed of the solution. The thickness uniformity of the thinfilm, evaluated by spectroscopic ellipsometry and by high-resolution x-ray reflectivity,remains constant through the thinning process. Moreover, the film roughness, analyzed byatomic force microscopy, slightly improves during the thinning process. The residual stressin the thin film is much smaller than that obtained by sacrificial oxidation. Mobility,measured by means of a bridge-type Hall bar on 15 nm film, is not significantlyreduced compared to the value of bulk silicon. Finally, the thinned SOI waferswere used to fabricate Schottky-barrier metal-oxide-semiconductor field-effecttransistors with a gate length down to 30 nm, featuring state-of-the-art current driveperformance.

Physics based modelling of short-channel nanowire MOSFET

A modelling framework for short channel nanowire (NW) MOSFETs that covers a wide range of operating conditions is presented. The device electrostatics in the subthreshold regime is dominated by the inter-electrode capacitive coupling, which, in the case of double gate (DG) devices, is analyzed in terms of conformal mapping techniques. Previously, we have shown that these results can also be successfully applied to the NW MOSFET, by performing an appropriate mapping to compensate for the difference in gate control between the two devices. Near and above threshold, the influence of the electronic charge is taken into account in a precise, self-consistent manner by combining suitable model expressions with Poisson's equation. The models are verified by comparison with numerical device simulations.

Input noise modelling of deep submicron MOSFETs

This paper presents a noise model using the channel length modulation (CLM) effect to calculate the total equivalent noise current, referred to the gate (input) of the MOSFET. It is shown here that for short channel MOSFETs the total input noise depends on the electron warming in the channel, the voltage fluctuations due to the gate polysilicon resistance, and the induced thermal noise at the gate. Taking velocity saturation effect and carrier heating effect in the gradual channel region, complete thermal noise modelling of short-channel MOSFETs including the induced gate noise and its correlation coefficients is presented.

Carrier backscattering characteristics of strained silicon-on-insulator n-MOSFETs featuring silicon–carbon source/drain regions

This work investigates for the first time, the physics of carrier transport in a sub-90 nm strained silicon-on-insulator (SOI) n-MOSFET with silicon–carbon (Si:C) source/drain (S/D) regions. The insertion of Si:C in the S/D exerts a lateral tensile strain in the transistor channel, leading to appreciable drive current enhancement. Significant improvement in both carrier backscattering r sat and source injection velocity υ inj were observed, accounting for the large drive current I Dsat enhancement in Si:C S/D transistors. This improvement becomes more appreciable as the gate length is reduced. The reduction in r sat is related to a shorter critical length ℓ 0 for carrier backscattering. On the other hand, the splitting of six-fold degenerate conduction band valleys due to strain-induced effects results in a reduced in-plane transport mass and thus contributes to significant υ inj enhancement. In addition, the dependence of drive current performance on source injection velocity and ballistic efficiency in a short channel MOSFET is also discussed.

Experimental evidence of mobility enhancement in short-channel ultra-thin body double-gate MOSFETs by magnetoresistance technique

Double-gate transistor with ultra-thin body (UTB) has proved to offer advantages over bulk device for high-speed, low-power applications. There is thus a strong need to obtain an accurate understanding of carrier transport and mobility in such device. In this work, we report for the first time an experimental evidence of mobility enhancement in UTB double-gate (DG) MOSFETs using magnetoresistance mobility extraction technique. Mobility in planar DG transistor operating in single- and double-gate mode is compared. The influence of different scattering mechanisms in the channel is also investigated by obtaining mobility values at low temperatures. The results show a clear mobility improvement in double-gate mode compared to single-gate mode mobility at the same inversion charge density. This is explained by the role of volume inversion in ultra-thin body transistor operating in DG mode. Volume inversion is found to be especially beneficial in terms of mobility gain at low-inversion densities.

A Reliable Metric for Mobility Extraction of Short-Channel MOSFETs

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> When comparing the extracted carrier mobility of long- and short-channel transistors, special consideration must be given to the metallurgical gate length <formula formulatype="inline"><tex>$(L_{\rm met})$</tex></formula>, neglecting the impact of source and drain junction profiles. <formula formulatype="inline"><tex>$L_{\rm met}$</tex> </formula> can be identified with nanometer precision by using RF split-<formula formulatype="inline"><tex>$C$</tex> </formula>–<formula formulatype="inline"><tex>$V$</tex></formula> measurements, and physical and electrical analysis can demonstrate the accuracy of the method. Another important parameter, the external transistor resistance <formula formulatype="inline"><tex>$(R_{\rm sd})$</tex></formula>, can be identified with linear current measurements of short-channel devices. However, it is important to quantify the mobility dependence from the gate length in order to obtain an accurate result. A method to estimate the electrical field <formula formulatype="inline"><tex>$(E_{\rm eff})$</tex></formula> of short-channel devices is proposed. The extracted short-channel mobility shows a universal behavior identical to the classical long-channel one. </para>

Modeling, verification and comparison of short-channel double gate and gate-all-around MOSFETs

Models for short-channel DG and GAA MOSFETs are presented. In the subthreshold regime, the electrostatics of the device is dominated by the capacitive coupling between the electrodes, which is analyzed by conformal mapping techniques. In the strong inversion regime, the device behavior is dominated by the inversion charge, allowing a 1D analysis. The models are verified by comparison with numerical device simulations. The electrostatic properties of the DG and GAA are compared, demonstrating the superior short-channel behavior of the GAA design.

Hot Carrier Effects in Wireless Communication Systems Built on Short-Channel MOSFETs

Phase noise is a critical factor that degrades the synchronization performance of a wireless communication receiver. Hot-carriers (HCs), found in the CMOS synchronization devices, are high-energy charge-carriers that can degrade the MOSFETs performance by damaging the internal device structure and lead to the phase noise increase therein. Such incremental phase noise can be related to the essential parameter, namely the MOSFET threshold voltage due to the HC effect, which is particularly evident in the short-channel MOSFET devices. In this letter, we analyze the impact of the phase noise arising from the HC effect on the wireless systems in terms of the bit-error-rate (BER) and the signal-to-interference-plus-noise ratio (SINR).

An analytical channel thermal noise model for deep-submicron MOSFETs with short channel effects

In this work, an analytical channel thermal noise model for short channel MOSFETs is derived. The transfer function of the noise was derived by following the Tsividis’ method. The proposed model takes into account the channel length modulation, velocity saturation, and carrier heating effects in the gradual channel region. Modeling results show good agreements with the measured noise data.

Enhancement-Mode Buried-Channel $\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As/In}_{0.52}\hbox{Al}_{0.48}\hbox{As}$ MOSFETs With High- $\kappa$ Gate Dielectrics

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> The operation of long- and short-channel enhancement-mode <formula formulatype="inline"> <tex>$\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$</tex></formula>-channel MOSFETs with high-<formula formulatype="inline"><tex>$\kappa$</tex></formula> gate dielectrics are demonstrated for the first time. The devices utilize an undoped buried-channel design. For a gate length of 5 <formula formulatype="inline"> <tex>$\mu\hbox{m}$</tex></formula>, the long-channel devices have <formula formulatype="inline"><tex>$V_{t} = + \hbox{0.25}\ \hbox{V}$</tex></formula>, a subthreshold slope of 150 mV/dec, an equivalent oxide thickness of 4.4 <formula formulatype="inline"><tex>$+/-$</tex></formula> 0.3 nm, and a peak effective mobility of 1100 <formula formulatype="inline"><tex>$\hbox{cm}^{2}/\hbox{V} \cdot \hbox{s}$</tex></formula>. For a gate length of 260 nm, the short-channel devices have <formula formulatype="inline"><tex>$V_{t} = + \hbox{0.5}\ \hbox{V}$</tex> </formula> and a subthreshold slope of 200 mV/dec. Compared with Schottky-gated high-electron-mobility transistor devices, both long- and short-channel MOSFETs have two to four orders of magnitude lower gate leakage. </para>

High dose Implantation Impact on the Carrier Mobility in Ultra-Thin Unstrained and Strained SOI Films

Based on electrical measurements and transmission electron microscopy imaging we propose in this paper a possible explanation for the measured mobility degradation with gate length reduction in short-channel MOSFETs. The carrier mobility in end-of-range implantation regions was investigated in Silicon-On-Insulator (SOI) and tensily-strained Silicon-On- Insulator (sSOI) substrates. Wafers with ultrathin films (from 8 to 35 nm) were Ge implanted at various concentrations, then annealed. The Pseudo-MOSFET measurements showed a mobility decrease (from 5 to 34%) as the implantation dose increased. The results are relevant for the optimization of the sources and drains regions of advanced nano-scale SOI transistors.

A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain

In this paper, an analytical model for threshold voltage of short-channel MOSFETs is presented. For such devices, the depletion regions due to source/drain junctions occupy a large portion of the channel, and hence are very important for accurate modeling. The proposed threshold voltage model is based on a realistic physically-based model for the depletion layer depth along the channel that takes into account its variation due to the source and drain junctions. With this, the unrealistic assumption of a constant depletion layer depth has been removed, resulting in an accurate prediction of the threshold voltage. The proposed model can predict the drain induced barrier lowering (DIBL) effect and hence, the threshold voltage roll-off characteristics quite accurately. The model predictions are verified against the 2-D numerical device simulator, DESSIS of ISE TCAD.

Subthreshold surface potential and drain current models for short-channel pocket-implanted MOSFETs

An analytical subthreshold surface potential model for short-channel pocket-implanted (double-halo) MOSFET is presented. The effect of the depletion layers around the source and drain junctions on channel depletion layer depth, which is very important for short-channel devices, is included. Using this surface potential, a drift-diffusion based analytical subthreshold drain current model for short-channel pocket-implanted MOSFETs is also proposed. A physically-based empirical modification of the channel conduction layer thickness that was originally proposed for relatively long-channel conventional device is made for such short-channel double-halo devices. Very good agreement for both the surface potential and drain current is observed between the model calculation and the prediction made by the 2-D numerical device simulation using Dessis.