Short-channel MOSFETs Research Articles

The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs) in the radio frequency (RF) regime. This paper describes the design of RF LNAs using a geometric programming (GP) optimization method. An important challenge for RF LNAs designed at nanometer scale geometries is the excess thermal noise observed in the MOSFETs. An extensive survey of analytical models and experimental results reported in the literature is carried out to quantify the issue of excessive thermal noise for short-channel MOSFETs. Short channel effects such as channel-length modulation and velocity saturation effects are also accounted for in our optimization process. The GP approach is able to efficiently calculate the globally optimum solution. The approximations required to setup the equations and constraints to allow convex optimization are detailed. The method is applied to the design of inductive source degenerated common source amplifiers at the 90 nm and 180 nm technology nodes. The optimization results are validated through comparison with numerical simulations using Agilent’s Advanced Design Systems (ADS) software.

A two-dimensional analytical model for short channel junctionless double-gate MOSFETs

A physics-based analytical model of electrostatic potential for short-channel junctionless double-gate MOSFETs (JLDGMTs) operated in the subthreshold regime is proposed, in which the full two-dimensional (2-D) Poisson’s equation is solved in channel region by a method of series expansion similar to Green’s function. The expression of the proposed electrostatic potential is completely rigorous and explicit. Based on this expression, analytical models of threshold voltage, subthreshold swing, and subthreshold drain current for JLDGMTs were derived. Subthreshold behavior was studied in detail by changing different device parameters and bias conditions, including doping concentration, channel thickness, gate length, gate oxide thickness, drain voltage, and gate voltage. Results predicted by all the analytical models agree well with numerical solutions from the 2-D simulator. These analytical models can be used to investigate the operating mechanisms of nanoscale JLDGMTs and to optimize their device performance.

On the importance of electron–electron scattering for hot-carrier degradation

Using our physics based model for hot-carrier degradation (HCD) we analyze the importance of the effect of electron–electron scattering (EES) on HCD in transistors with different channel lengths. The model is based on a thorough treatment of carrier transport and is implemented into the deterministic Boltzmann transport equation solver ViennaSHE. Two competing mechanism of Si–H bond-breakage are captured by the model: the one triggered by the multiple vibrational excitation of the bond and another which is due to excitation of one of the bonding electrons to an antibonding state by a solitary hot carrier. These processes are considered self-consistently as competing pathways of the same dissociation reaction. To analyze the importance of the EES process we use a series of nMOSFETs with identical architecture but different gate lengths. The gate length varies in the wide range of 44–300 nm to cover short-channel MOSFETs as well as their longer counterparts. According to previous findings, EES starts to become important at a channel length of 180 nm. This situation is captured in the targeted gate length interval. Our results show that the channel length alone is not a sufficient criterion on the importance of EES and that the applied bias conditions have to be taken into account as well.

A New Highly Accurate CMOS Current-Mode Four-Quadrant Multiplier

A new CMOS current-mode four-quadrant analog multiplier is presented. The design is based on the square-difference approach using short-channel MOSFETs operating in saturation region and a rectifier. The squaring circuit used is free of error due to carrier mobility reduction and hence an accurate multiplier is achieved. Tanner T-spice is used to confirm the functionality of the proposed design using 0.18μm TCMS CMOS process technology. Simulation results shows that the relative error is 1.8% and –3dB frequency is 230MHz.

Unified Transient and Frequency Domain Noise Simulation for Random Telegraph Noise and Flicker Noise Using a Physics-Based Model

Unified transient and frequency domain noise simulation of random telegraph noise and flicker noise is conducted using a multiphonon-assisted model that considers tunneling probabilities and energy transitions of discretized traps in the gate insulator of MOSFETs. The proposed model is able to concurrently represent the dynamic behavior of electron and hole trapping and detrapping via interactions with both the Si substrate and Poly-Si gate. The model is implemented in a 3-D device simulator to examine the effect of device structure and bias conditions. The conventional analytical model does not precisely estimate the noise powers in short-channel MOSFETs due to the nonuniform trapped charge effect. The high trap density near the shallow trap isolation edges is predicted quantitatively by comparing the measured data with the simulated data. In conclusion, we confirm the validity of the developed unified simulator and its usefulness for gaining insights into trap sites and noise reduction engineering.

English

In this paper, a simple general yet realistic MOSFET model named nth power law MOSFET model for I-V characteristic of MOSFET in linear and saturation region is proposed. Model can express I-V characteristics of short channel MOSFET’S at least down to 0.12-μm channel length and resistance inserted MOSFET. The model evaluation time is about 1/3 of the evaluation time of the SPICE MOS LEVEL-1model. The model parameter extraction is done by solving single variable equations .solution can be done within a second, being different from the fitting procedure with expensive numerical iterations employed for the conventional models. Model plays a role of a bridge between a complicated MOSFET current characteristics and circuit behaviour in the deep sub -micrometer region.

CMOS-Compatible Self-Aligned In<sub>0.53</sub>Ga<sub>0.47</sub>As MOSFETs With Gate Lengths Down to 30 nm

We demonstrate self-aligned fully-depleted 20-nm-thick In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As-channel MOSFETs using CMOS-compatible device structures and manufacturable process flows. These devices consist of self-aligned source/drain extensions and self-aligned raised source/drain with low sheet resistance of 360 and 115 Ω/sq, respectively. We demonstrate short-channel MOSFETs with gate lengths L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> down to 30 nm, low series resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EXT</sub> = 375 Ω·μm, and high peak saturation transconductance G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MSAT</sub> = 1275 μS/μm at L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = 50 nm and drain bias V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V. We obtain long-channel capacitive inversion thickness TINV = 2.3 nm and effective mobility μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EFF</sub> = 650 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs at sheet carrier density N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> = 5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> . Finally, using a calibrated quasi-ballistic FET model, we argue that for L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ≤ 20 nm, μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EFF</sub> ≈ 1000 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs will lead to short-channel MOSFETs operating within 10% of the ballistic limit. Thus, our III-V processes and device structures are well-suited for future generations of high-performance CMOS applications at short gate lengths and tight gate pitches.

A Short-Channel Common Double-Gate MOSFET Model Adapted to Gate Oxide Thickness Asymmetry

Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this paper, we demonstrate that using the unique quasi-linear relationship between the surface potentials, it is possible to develop compact model for CDG-MOSFETs without such approximation while preserving the mathematical complexity at the same level of the existing models. In the proposed model, the surface potential relationship is used to include the drain-induced barrier lowering, channel length modulation, velocity saturation, and quantum mechanical effect in the long-channel model and good agreement is observed with the technology computer aided design simulation results.

An optimized junctionless GAA MOSFET design based on multi-objective computation for high-performance ultra-low power devices

An analytical investigation has been proposed to study the subthreshold behavior of junctionless gates all around (JLGAA) MOSFET for nanoscale CMOS analog applications. Based on 2-D analytical analysis, a new subthreshold swing model for short-channel JLGAA MOSFETs is developed. The analysis has been used to calculate the subthreshold swing and to compare the performance of the investigated design and conventional GAA MOSFET, where the comparison of device architectures shows that the JLGAA MOSFET exhibits a superior performance with respect to the conventional inversion-mode GAA MOSFET in terms of the fabrication process and electrical behavior in the subthreshold domain. The analytical models have been validated by 2-D numerical simulations. The proposed analytical models are used to formulate the objectives functions. The overall objective function is formulated by means of a weighted sum approach to search the optimal electrical and dimensional device parameters in order to obtain the better scaling capability and the electrical performance of the device for ultra-low power applications.

A CMOS current-mode squaring circuit free of error resulting from carrier mobility reduction

This paper presents a new current-mode squaring circuit. The design is based on MOSFETs translinear principle in strong inversion. A new compensation technique to minimize the second order effects caused by carrier mobility reduction in short channel MOSFETs is proposed. Tanner T-spice simulation tool is used to confirm the functionality of the proposed design in 0.18 µm CMOS process technology. Simulation results indicate that the maximum linearity error is 1.2 %; power consumption is 326 µW and bandwidth of 340 MHz.

Subthreshold behavior models for short-channel junctionless tri-material cylindrical surrounding-gate MOSFET

A novel junctionless tri-material cylindrical surrounding-gate (JLTMCSG) MOSFET is presented in this paper. The subthreshold behavior of JLTMCSG MOSFET is investigated by developing physical based analytical models for channel electrostatic potential, horizontal electric field, and subthreshold current. It is revealed that JLTMCSG MOSFET can effectively suppress DIBL and simultaneously improve carrier transport efficiency. It is also found that subthreshold current for JLTMCSG MOSFET can be significantly reduced by adopting both a small oxide thickness and a thin silicon channel. The accuracy of analytical model is verified by its good agreement with the three-dimensional numerical device simulator ISE.

Analysis of Carrier Transport in Short-Channel MOSFETs

A method for extracting transport parameters in short-channel FETs is presented in the context of the Lundstrom model for quasi-ballistic short-channel FETs. The parameters extracted from measured data are unidirectional thermal velocity, critical length, and mean free path at low and high drain biases. The method is based on an analysis of the channel length dependence of apparent mobility and virtual-source (VS) velocity, which are obtained by fitting the VS model to measured data. Data from (100)-oriented undoped-body extremely thin silicon-on-insulator FETs with neutral stress liners are used to validate the method. Since this method does not assume any theoretical knowledge of band structure parameters, it can be applied to short-channel FETs with any geometry, any channel material, and with unknown levels of channel stress.

Compact Model for Short-Channel Junctionless Accumulation Mode Double Gate MOSFETs

A 2-D closed form, analytical compact model for long- and short-channel junctionless accumulation mode double gate MOSFETs is presented. The physics-based 2-D model for the potential is derived with the help of Poisson's equation and the conformal mapping technique by Schwarz-Christoffel. From this closed-form solution, we derive simple equations for the calculation of the threshold voltage VT and subthreshold slope S. Using Lambert's W-function and a smoothing function for the transition between the depletion and accumulation regions, a unified charge model valid for all operating regimes is developed. Dependencies between the physical device parameters and their impact on the device performance are worked out. A comparison of our 2-D physics-based compact model is done versus 2-D technology computer-aided design (TCAD) Sentaurus simulation data.

Accurate Non-Quasi-Static Gate-Source Impedance Model of RF MOSFETs

An improved non-quasi-static gate-source impedance model including a parallel RC block for short-channel MOSFETs is developed to simulate RF MOSFET input characteristics accurately in the wide range of high frequency. The non-quasi-static model parameters are accurately determined using the physical input equivalent circuit. This improved model results in much better agreements between the measured and modelled input impedance than a simple one with a non-quasi-static resistance up to 40GHz, verifying its accuracy.

Compact drain-current model for undoped cylindrical surrounding-gate metal-oxide-semiconductor field effect transistors including short channel effects

In this paper, we present a compact model for undoped short-channel cylindrical surrounding-gate MOSFETs. The drain-current model is expressed as a function of the mobile charge density, which is calculated using the analytical expressions of the surface potential and the difference between surface and center potentials model. The short-channel effects are well incorporated in the drain-current model, such as the drain-induced barrier lowering, the charge sharing effect (VT Roll-off), the subthreshold slope degradation, and the channel length modulation. A comparison of the model results with 3D numerical simulations using Silvaco Atlas-TCAD presents a good agreement from subthreshold to strong inversion regime and for different bias voltages.

Quantitative Extraction of Electric Flux in the Buried-Oxide Layer and Investigation of Its Effects on MOSFET Characteristics

Silicon-on-insulator (SOI) MOSFETs have advantages over conventional bulk MOSFETs in terms of their electrical characteristics, but also have inherent disadvantages due to the presence of their buried-oxide (BOX) layers. In this paper, focus was placed on drain electric flux passing via the BOX layer to the body region as an influence that induces disadvantages such as drain-induced barrier lowering in SOI MOSFETs. The electric flux in the BOX layer was visualized using stream functions, and was quantitatively evaluated for the first time ever. The results showed the dependence of electric flux on relative permittivity and the BOX layer thickness. These outcomes confirmed that the subthreshold slope (SS) in short-channel SOI MOSFETs is affected strongly by electric flux detouring via the BOX layer, and the compact model of the enhancement of SSs due to the flux is proposed.

Negative differential resistance and effect of defects and deformations in MoS2 armchair nanoribbon metal-oxide-semiconductor field effect transistor

In this work, we present a study on the negative differential resistance (NDR) behavior and the impact of various deformations (like ripple, twist, wrap) and defects like vacancies and edge roughness on the electronic properties of short-channel MoS2 armchair nanoribbon MOSFETs. The effect of deformation (3°–7° twist or wrap and 0.3–0.7 Å ripple amplitude) and defects on a 10 nm MoS2 ANR FET is evaluated by the density functional tight binding theory and the non-equilibrium Green`s function approach. We study the channel density of states, transmission spectra, and the ID–VD characteristics of such devices under the varying conditions, with focus on the NDR behavior. Our results show significant change in the NDR peak to valley ratio and the NDR window with such minor intrinsic deformations, especially with the ripple.

亚90 nm沟道MOSFET亚阈值状态下二维电势和阈值电压的半解析模型

A A 2D semi-analytical model for electric potential and threshold voltage of the sub-90 nm channel MOSFET in subthreshold state is presented in this paper. First, a de nite problem is given according to the physical model of the Short Channel MOSFET in sub-threshold state, and then the transcendental equations obtained by using the connected condition of oxide layer and space charge region are expanded by the charac- teristic function. The results are linear algebraic equations about unknown quantities. The 2D electric potential expressions of oxide layer and space charge region, depletion thickness and threshold voltage are obtained by the model. The model is free of adapter parameters, its calculation amount is small, the equation discretion is avoided and the result is as accurate as the numerical solution. The potential distribution, surface potential, depletion thickness and threshold of the MOSFET whose channel length is shorter than 90 nm have been calculated in this paper. It is shown that the calculated results are highly coincident with the 2D numerical simulations.

Quantum Analytical Model for Inversion Charge and Threshold Voltage of Short-Channel Dual-Material Double-Gate SON MOSFET

Our previous work analytically establishes that silicon-on-nothing (SON) is superior to silicon-on-insulator MOSFET because of its higher immunity to different short-channel effects and increased current driving capability. Moreover, it has also been shown that our analytical model agrees with various simulation results obtained from MEDICI, ATLAS 2-D, and so on. Because of the ultrathin device structure, classical models are not sufficient to determine accurately potential profile, threshold voltage, or charge inversion phenomena for dual-material double-gate (DMDG) SON MOSFET. Hence, in this paper, for the first time, carrier quantization arising due to the ultrathin body has been included to develop an analytical model for ultrathin low-dimensional DMDG SON structure. The 2-D Poisson and 1-D Schrodinger equations have been solved under the dual-material front gate to find the overall potential and inversion charge profile. The deviation of the quantum threshold voltage from the classical one has been calculated and added to the classical threshold voltage to get its quantum counterpart. The proposed model has also been validated against the numerical device simulator ATLAS 2-D.

A Continuous Regional Current-Voltage Model for Short-channel Double-gate MOSFETs

A continuous, explicit drain-current equation for short-channel double-gate (DG) MOSFETs has been derived based on the explicit surface potential equation. The model is physically derived from Poisson’s equation in each region of operation and adopted in the unified regional approach. The proposed model has been verified with numerical solutions, physically scalable with channel length and gate/oxide materials as well as oxide/channel thicknesses.