Short-channel MOSFETs Research Articles

Analytical threshold voltage model for short-channel asymmetrical dual-gate material double-gate MOSFETs

For a symmetrical DG MOSFET with two different gate-metals with two work functions, ?m1 and ?m2, a threshold voltage model is derived and presented for different L1/L2 ratios. The solid lines correspond to the model results and the symbols to the simulation results. An analytical threshold voltage model in undoped short-channel DG MOSFETs with asymmetrical dual gate material is presented. The threshold voltage model is derived based on an analytical solution for the potential distribution along the channel in the subthreshold region. For verification of the model, the potential distribution along the channel length and the threshold voltage are compared with simulation results for a wide range of the device dimensions.

On the Noise Optimization of CMOS Common-Source Low-Noise Amplifiers

In this paper, we propose a general noise optimization technique for the CMOS common-source low-noise amplifiers. By directly employing the short-channel MOSFET - characteristic and van der Ziel's noise model, we derive design equations for the selection of the circuit design parameters, such as transistor sizes, passive component values, and bias voltages, which are subject to various gain and current consumption constraints. We also include several side effects, including the finite quality factor and the back-gate transconductance into the optimization process, and analyze their impact on the optimization results. Design examples that are based on a virtual but realistic process are given to verify our analysis and to give design intuition.

Effect of Localized Interface Charge on the Threshold Voltage of Short-Channel Undoped Symmetrical Double-Gate MOSFETs

An analytical threshold-voltage model of short-channel undoped symmetrical double-gate metal-oxide-semiconductor field-effect transistors including positive or negative interface charges near the drain is presented. The threshold-voltage model is derived based on an analytical solution for the potential distribution along the channel in the subthreshold region. Both potential and threshold-voltage models are compared with the Atlas simulation results, with variables being the device dimensions, the interface-charge region length and the interface-charge density. A good agreement between the model and simulation results has been observed by calibrating as a constant parameter the gate voltage included in the position of the minimum potential and the carrier charge-sheet density at the potential minimum that is adequate to achieve the turn-on condition.

Qualitative analysis of excess noise in nanoscale MOSFET

Recent experiment indicates that shot noise is the dominant excess noise in nanoscale MOSFET. However the early research reported that no shot noise was observed in MOSFET, and thermal noise was the excess noise in short channel MOSFET. Based on the device current model, we derive the conversion conditions for the dominant component of excess noise shifting from thermal noise to shot noise. According to the conversion conditions, the prediction of the noise performance of nanoscale MOSFET is given, and the results coincide with experimental phenomena, simulation data and conclusion of mesoscopic shot noise, which has been reported in the article.

Characterization of Series Resistance and Mobility Degradation Parameter and Optimizing Choice of Oxide Thickness in Thin OxideN-Channel MOSFET

We present two methods to extract the series resistance and the mobility degradation parameter in short-channel MOSFETs. The principle of the first method is based on the comparison between the exponential model and the classical model of effective mobility and for the second method is based on directly calculating the two parameters by solving a system of two equations obtained by using two different points in strong inversion at small drain bias from the characteristic (). The results obtained by these techniques have shown a better agreement with data measurements and allowed in the same time to determine the surface roughness amplitude and its influence on the maximum drain current and give the optimal oxide thickness.

Analytical threshold voltage model for lightly doped short-channel tri-gate MOSFETs

A simple analytical threshold voltage model for lightly doped tri-gate MOSFETs has been developed, using the superposition of the threshold voltages of a symmetric and an asymmetric double-gate MOSFET. The model has been verified by comparison with experimental and simulation results of tri-gate FinFETs with various fin widths and channel lengths. Excellent agreement between model, experimental and simulation results is obtained, demonstrating the validity of the proposed threshold voltage model.

Schrödinger-equation-based quantum corrections addressing degeneracy-breaking and confinement-enhanced scattering

We review extensions of Schrodinger-equation-based quantum corrections that have been implemented within the semiclassical Monte Carlo simulator Monte Carlo of The University of Texas (MCUT) to address quantum-confinement-induced redistribution of carriers in momentum as well as real space, and confinement-enhanced scattering in n-channel MOSFETs. The significance of these quantum confinement effects and of these corrections has been illustrated via calculation of channel mobility and short-channel MOSFET drive currents for strained and unstrained devices.

Barrier Lowering and Backscattering Extraction in Short-Channel MOSFETs

In this paper, we propose a fully experimental method to extract the barrier lowering in short-channel saturated MOSFETs using the Lundstrom backscattering transport model in one-subband approximation and carrier degeneracy. The knowledge of barrier lowering at the operative bias point in the inversion regime is of fundamental importance in device scaling. At the same time, we also obtain an estimate of the backscattering ratio and the saturation inversion charge. With respect to previously reported works on extraction of transport parameters based on the Lundstrom model, our extraction method is fully consistent with it, whereas other methods make a number of approximations in the calculation of the saturation inversion charge, which are inconsistent with the model. The proposed experimental extraction method has been validated and applied to results from device simulation and measurements on short-channel poly-Si/SiON gate nMOSFETs with gate lengths down to 70 nm. Moreover, we propose an extension of the backscattering model to the case of 2-D geometries (e.g., bulk MOSFETs). We found that, in this case, backscattering is governed by the carrier transport in a few nanometers close to the silicon/oxide interface and that the value of the backscattering ratio obtained with a 1-D approach can be significantly different from the real 2-D value.

Effects of Substrate Orientation and Channel Stress on Short-Channel Thin SOI MOSFETs

We present a study of the effects of substrate orientation and longitudinal channel stress on the performance of extremely thin silicon-on-insulator (ETSOI) MOSFETs with gate lengths down to 25 nm. We find that short-channel electron and hole mobilities follow the long-channel mobility trends versus substrate orientation and longitudinal channel stress. We show that with respect to (100) silicon-on-insulator (SOI) substrates, short-channel ETSOI MOSFETs on (110) SOI substrates lead to 25% enhancement of the p-channel FET drive current at the expense of 12% degradation of the n-channel FET drive current at a fixed off-current of 100 nA/μm and a supply voltage of 1 V. Finally, we estimate that an ETSOI complementary metal-oxide-semiconductor (CMOS) on (110) SOI substrates should lead to 10% faster ring oscillators compared with those on (100) SOI wafers, which also implies that (100)-oriented wafers with (110) sidewalls are a better choice for fabricating nonplanar FinFETs and trigate CMOS circuits.

Radiation Effect Evaluation in Effective Short and Narrow Channels of LDD Transistor With LOCOS Isolation Using OTCP Method

In this paper, we have presented a new methodology to take out the local oxidation of silicon (LOCOS) and lightly doped drain (LDD) subdiffusion effects from charge-pumping (CP) curves, leaving only the CP current of the effective channel, in narrow- and short-channel MOSFET transistors. First, we have clarified the contribution of LDD-subdiffusion and LOCOS regions to the CP characteristics by studying the spatial distributions of CP threshold and flatband voltages. We have shown that the maximum CP current is the contribution of pumped current in the effective-channel, LOCOS, and LDD-subdiffusion regions. Second, we have successfully used the oxide-trap CP (OTCP) to extract the radiation-induced oxide trap (?N ot) and interface trap (?N it) in effective short- and narrow-channel transistors. Finally, we have performed a comparison between the OTCP and the capacitance-versus-voltage method.

Mobility enhancement by CESL strain in short-channel ultrathin SOI MOSFETs

The electrical properties of front and back channels in advanced SOI MOSFETs (ultrathin film, short length, metal-gate/high-K stack, thin BOX) are used to reveal the impact of tensile and compressive CESL strain. The benefit of compressive strain is maximized in 100nm long MOSFETs, where the hole mobility can be increased by a factor of two. In shorter devices, the mobility gain fades away due to neutral defects and remote Coulomb scattering. The short-channel scattering and strain mechanisms are identified by low temperature measurements and explained by an original physics-based model.

Compact subthreshold current and capacitance modeling of short-channel double-gate MOSFETs

A precise two-dimensional subthreshold current and capacitance modeling of short-channel, nanoscale double-gate MOSFETs is presented. The model covers a wide range of geometries and material combinations. The subthreshold model is based on conformal mapping techniques. The results are in excellent agreement with numerical simulations.

Transformation Between Power-law and Polynomial Thin-Film Transistor Models

A procedure is proposed to convert back and forth between two equations used to model the saturation current of thin film transistors. To demonstrate and determine the effectiveness of the proposed procedure, experimental data modeled by the traditional monomial (power-law) model is transformed into a recently proposed polynomial model. Conversely, another set of data, which was originally represented by the polynomial model, is transformed to the monomial model. This procedure is also applied to short-channel crystalline MOSFETs.

A Simple Semiempirical Short-Channel MOSFET Current–Voltage Model Continuous Across All Regions of Operation and Employing Only Physical Parameters

A simple semiempirical model I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> , V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> ) for short-channel MOSFETs applicable in all regions of device operation is presented. The model is based on the so-called ldquotop-of-the-barrier-transportrdquo model, and we refer to it as the ldquovirtual sourcerdquo (VS) model. The simplicity of the model comes from the fact that only ten parameters are used. Of these parameters, six are directly obtainable from standard device measurements: 1) gate capacitance in strong inversion conditions (typically at maximum voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> ); 2) subthreshold swing; 3) drain-induced barrier lowering (DIBL) coefficient; 4) current in weak inversion (typically I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 0 V) and at high V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> ; 5) total resistance at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0 V and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> and 6), effective channel length. Three fitted physical parameters are as follows: 1) carrier low-field effective mobility; 2) parasitic source/drain resistance, 3) the saturation region carrier velocity at the so-called virtual source. Lastly, a constrained saturation-transition-region empirical parameter is also fitted. The modeled current versus voltage characteristics and their derivatives are continuous from weak to strong inversion and from the linear to saturation regimes of operation. Remarkable agreement with published state-of-the-art planar short-channel strained devices is demonstrated using physically meaningful values of the fitted physical parameters. Moreover, the model allows for good physical insight in device performance properties, such as extraction of the VSV, which is a parameter of critical technological importance that allows for continued MOSFET performance scaling. The simplicity of the model and the fact that it only uses physically meaningful parameters provides an easy way for technology benchmarking and performance projection.

Compact Subthreshold Current Modeling of Short-Channel Nanoscale Double-Gate MOSFET

A physics-based compact subthreshold current model for short-channel nanoscale double-gate MOSFETs is presented. The potential is modeled using conformal mapping techniques in combination with parabolic approximations. For subthreshold conditions, we have assumed that the electrostatics is dominated by capacitive coupling between the body electrodes. Hence, the potential is obtained as an analytical solution of the 2-D Laplace equation. The current modeling is based on drift-diffusion theory. The modeling results are in good agreement with those of numerical simulations without the use of adjustable parameters.

A compact drain current model of short-channel cylindrical gate-all-around MOSFETs

A fully analytical potential model, valid in the weak inversion regime of short-channel cylindrical gate-all-around (GAA) MOSFET, is proposed. The model derivation is based on a previous analytical expression for tetragonal GAA MOSFET and the rotational symmetry of the tetragonal cross section. Device simulations were performed to verify that the potential distribution along the channel is properly described in all positions within the silicon body. Using the potential model, analytical expressions for the threshold voltage, subthreshold swing and drain-induced barrier lowering have been derived. Including the short-channel effects within an existing model for the subthreshold leakage current and an analytical drain current model of long-channel devices in strong inversion, a compact drain current model has been derived describing with good accuracy the transfer and output characteristics of short-channel GAA MOSFETs in all regions of operation.

Advanced Design Methodology of High-Performance Sub-100-nm-Channel GAA MOSFET

This paper reconsiders the design methodology of the short-channel GAA SOI MOSFET and proposes an advanced concept to enhance its performance. The new ideas are based on gate field engineering and source and drain diffusion engineering. Validity of the proposal is demonstrated by device simulations

Compact model of short-channel MOSFETs considering quantum mechanical effects

A unified analytical model for the I–V characteristics of short channel bulk nMOSFETs with 〈100〉 Si surface orientation valid for the subthreshold, linear and saturation regions is presented. In this model, the inversion layer charge is obtained considering quantum mechanical (QM) effects. The field dependent mobility variations, velocity saturation of carriers and secondary effects such as DIBL and channel length modulation have been incorporated in this model. There is a smooth transition in the current from subthreshold to above threshold and also from linear to saturation regions of operation. This results in highly continuous channel conductance (gds) and transconductance (gm), which are important circuit parameters in small signal analysis. In addition, the result of a few benchmark tests shows that the model holds good promise for analog circuit design. The model has been implemented in SABER, a circuit simulator. The result from the model shows an excellent agreement with two-dimensional device simulator and experimental data.

Compact subthreshold slope modelling of short-channel double-gate MOSFETs

A precise, compact, subthreshold slope model of short-channel nanoscale double-gate MOSFETs is presented. The model encompasses the effects of device dimensions, built-in voltages and bias voltages on the subthreshold slope. The subthreshold model is based on conformal mapping techniques. Results are in excellent agreement with numerical simulations.

Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design

In this paper, a compact channel thermal noise model for short-channel MOSFETs is presented and applied to the radio frequency integrated circuit (RFIC) design. Based on the analysis of the relationship among different short-channel effects such as velocity saturation effect (VSE), channel-length modulation (CLM), and carrier heating effect (CHE), the compact model for the channel thermal noise was analytically derived as a simple form. In order to simulate MOSFET's noise characteristics in circuit simulators, an appropriate methodology is proposed. The used compact noise model is verified by comparing simulated results to the measured data at device and circuit level by using 65nm and 130nm CMOS technologies, respectively.