UV nanoimprint lithography process optimization for electron device manufacturing on nanosized scale

Abstract

Imprint specific process parameters like the residual layer thickness and the etch resistance of the UV polymers for the substrate etch process have to be optimized to introduce UV nanoimprint lithography (UV NIL) as a high-resolution, low-cost patterning technique for research and industry into electron device manufacturing. Additionally, UV NIL processes have to be compatible with conventional silicon (Si) semiconductor processing. Within this work, the minimization of the residual layer thickness by using a multi-drop ink-jet system, which was integrated into the imprint stepper NPS300 from S-E-T-(formerly SUSS MicroTec), in combination with a low viscous UV polymer from Asahi Glass Company is shown. The etch resistance of different UV polymers against the poly-Si etch process was increased by 50% with an appropriate post-exposure bake. A poly-Si dry etch process was used to pattern the gates of short channel MOSFETs. After optimizing the poly-Si etch, properly working short channel MOSFETs with a minimum gate length of about 90 nm were fabricated demonstrating successfully the compatibility of UV NIL with conventional Si semiconductor processing on nanosized scale.