Abstract
Based on electrical measurements and transmission electron microscopy imaging we propose in this paper a possible explanation for the measured mobility degradation with gate length reduction in short-channel MOSFETs. The carrier mobility in end-of-range implantation regions was investigated in Silicon-On-Insulator (SOI) and tensily-strained Silicon-On- Insulator (sSOI) substrates. Wafers with ultrathin films (from 8 to 35 nm) were Ge implanted at various concentrations, then annealed. The Pseudo-MOSFET measurements showed a mobility decrease (from 5 to 34%) as the implantation dose increased. The results are relevant for the optimization of the sources and drains regions of advanced nano-scale SOI transistors.
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