Short-channel MOSFETs Research Articles

An analytic model for punchthrough-implanted MOSFETs in strong inversion

This paper presents an analytic model for punchthrough-implanted MOSFETs in strong inversion. The effect of channel and punchthrough implantation was studied based on Gaussian doping profiles. The threshold voltage, the body effect and the I ds - V ds characteristics were all solved analytically. Results were checked with both long-channel and short-channel MOSFETs, and show good agreement with experiments.

Indium channel implant for improved short-channel behavior of submicrometer NMOSFETs

Indium has been used as an alternative channel implant in submicrometer-channel Si MOSFETs in order to obtain highly nonuniform channel doping. Superior device characteristics have been obtained down to 0.17- mu m channel length. The device characteristics have been compared to those of uniform boron-implanted short-channel MOSFETs used in a 0.25- mu m CMOS technology. Results indicate that NMOSFETs with nonuniform channel doping obtained with indium have superior short-channel effect (SCE) when compared to NMOSFETs with uniformly (boron) doped channel. >

Defect localization induced by hot carrier injection in short-channel MOSFETs: Concept, modeling and characterization

Key aspects related to the localization of the hot-carrier induced damage in short channel MOSFET's are reviewed. Emphasis is put on the analysis, modeling and characterization of the degradation of device parameters caused by defects created locally beside the drain junction. Numerical simulations as well as analytical models predicting the post-stress performance are presented, compared and their limits of validity highlighted. Relevant experimental results, concerning the evolution of the static characteristics I D ( V G , V D ) during transistor aging, are thoroughly discussed and efficient methods for the extraction of the defective region parameters are proposed. More specific techniques (charge pumping, noise spectroscopy, floating gate current, gated diode leakage), used for the characterization of aging induced defects, are evaluated from the point of view of their capability to cope with the localized nature of the defects. The merits of silicon on insulator structures and other technological solutions proposed for the attenuation of hot carrier effects are briefly commented.

Transit-time model for short-channel MOSFET's

A new analytical transit-time model for submicrometer MOS devices has been developed. The model is based on a modified SPICE level-three MOSFET DC model, and it allows the use of a physical value for the charge carrier saturation velocity. This is essential for accurate transit-time modeling. Both DC and transit-time models show good agreement with the results obtained from more complicated two-dimensional numerical simulations. >

Simple Model for the Second Substrate Current Hump in Short-Channel LDD MOSFETs

Simple Model for the Second Substrate Current Hump in Short-Channel LDD MOSFETs

A simple two-dimensional model for subthreshold channel-length modulation in short-channel MOSFETs

A physical yet simple model that describes subthreshold channel-length modulation and its complex relationship with drain-induced barrier lowering (DIB) in short-channel MOSFETs is derived. The underlying quasi-two-dimensional analysis produced a V/sub DS/-independent value for the modulated channel length in weak inversion, which can be used to simplify and correct subthreshold current simulation. The model, supported by numerical device simulation, further gives insight regarding how channel-length modulation scales with structural parameters.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A nonpinchoff gradual channel model for deep-submicron MOSFET's

A drain current model for a short-channel MOSFET, which is named the nonpinchoff model, is proposed. In this model, the effect of the horizontal electric field is precisely taken into account to solve the two-dimensional Poisson's equation. The pinchoff point, where the horizontal electric field tends to infinity in the conventional gradual-channel approximation, disappears in the nonpinchoff model, so that linear and saturation regions are smoothly connected. As a result, the ambiguity of the boundary between the linear region and saturation region in a short channel MOSFET can be understood using a single equation for the drain current.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs

An analytical model for the subthreshold regime of operation of short-channel MOSFETs is presented, and expressions for the threshold-voltage shift associated with the drain-induced barrier lowering (DIBL) caused by the application of a drain bias are developed. The amount of drain-bias-induced depletion charge in the channel is estimated, and an expression for the distribution of this charge along the channel is developed. From this distribution, it is possible to find the lowering of the potential barrier between the source and the channel, and the corresponding threshold-voltage shift. The results are compared with experimental data for deep-submicrometer NMOS devices. Expressions for the subthreshold current and for a generalized unified charge control model (UCCM) for short-channel MOSFETs are presented. The theory is applicable to deep-submicrometer devices with gate lengths larger than 0.1 mu m. The model is suitable for implementation in circuit simulators.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Precise modeling of hot carrier gate current in short-channel MOSFET's

A powerful model which considers the fact that the values of the channel and carrier temperatures T and T/sub c/ vary with position in the bulk and channel is considered. It reveals that the energy distribution of hot carriers deviates from the well-known Maxwellian distribution by a small but nonnegligible perturbation and evaluates the dependence of this deviation of the device technology, geometry, and biasing conditions. The model helps to remove important discrepancies between the old hot-carrier models and measurements. >

A new 2-D analytic threshold-voltage model for fully depleted short-channel SOI MOSFET's

The exact solution of the 2-D Poisson equation for fully depleted SOI MOSFETs is derived by using a three-zone Green's function solution technique. Based on the derived 2-D potential distribution, the front and back surface potential distributions in the Si film are analytically obtained and their accuracies are verified by 2-D numerical analysis. The calculated minimum surface potential and its location are used to analyze the drain-induced barrier-lowering effect and further to develop an analytic threshold-voltage model. Comparisons between the developed analytic threshold-voltage model and the 2-D numerical analysis are made. It is shown that excellent agreements are obtained for wide ranges of device structure parameters and applied biases. >

Series resistance of self-aligned silicided source/drain structure

The external resistance of the self-aligned silicided source/drain structure is examined by two-dimensional simulation considering recession of the contact interface due to the consumption of silicon during the silicidation process. It is observed that the recessed contact interface forces a significant amount of current to flow into the high-resistivity part of the junction, resulting in an increase of resistance as large as several hundred ohms-micrometers in comparison with the surface contact structure. The increase scales up with the scaledown of the minimum feature size, and the expected benefits of the salicide structure diminish for the sub-half-micrometer devices. A simple analytical explanation is proposed. By considering the recession of the contact interface, the reported high external resistance of short-channel MOSFETs is explained. Different source/drain contact types are compared, and it is concluded that the conventional salicide process should be modified for sub-half-micrometer devices. >

An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation

An improved analytical model for short-channel MOSFETs which is valid in all regions of operation with both the continuous drain current and the output conductance by introducing a source-drain series resistance dependent scaling factor is proposed for analog/digital circuit simulation. This model considers all second-order effects for an accurate determination of the pinchoff point location without internal numerical iterations. Comparisons with experimental data for submicron devices confirm the model validity. Furthermore, a simple interpolation is also presented to maintain the continuous slope of the output conductance and its effect on the drain current is demonstrated to be acceptable.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The enhancement of gate-induced-drain-leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain beta

An off-state leakage current unique for short-channel SOI MOSFETs is reported. This off-state leakage is the amplification of gate-induced-drain-leakage current by the lateral bipolar transistor in an SOI device due to the floating body. The leakage current can be enhanced by as much as 100 times for 1/4 mu m SOI devices. This can pose severe constraints in future 0.1 mu m SOI device design. A novel technique was developed based on this mechanism to measure the lateral bipolar transistor current gain beta of SOI devices without using a body contact.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Effects of carrier-velocity saturation on the characteristics of short channel MOSFETs with lightly doped drains

physica status solidi (a)Volume 131, Issue 1 p. K77-K80 Short Note Effects of carrier-velocity saturation on the characteristics of short channel MOSFETs with lightly doped drains M. B. Lee, M. B. Lee Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Search for more papers by this authorJ. I. Lee, J. I. Lee Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Search for more papers by this authorK. N. Kang, K. N. Kang Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Search for more papers by this authorK. S. Yoon, K. S. Yoon Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Information Engineering Department, Korea University, Jochiwon, Chungnam 339–800, KoreaSearch for more papers by this authorS. Hong, S. Hong Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Electrical Engineering Department, Korea Advanced Institute ofence and Technology, 400, Kusong-Dong, Youson-Ku, Taejon 305–701, KoreaSearch for more papers by this authorK. Y. Lim, K. Y. Lim Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Physics Department, Jeonbuk National University, Jeonjoo, Jeonbuk 560–756, KoreaSearch for more papers by this author M. B. Lee, M. B. Lee Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Search for more papers by this authorJ. I. Lee, J. I. Lee Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Search for more papers by this authorK. N. Kang, K. N. Kang Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Search for more papers by this authorK. S. Yoon, K. S. Yoon Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Information Engineering Department, Korea University, Jochiwon, Chungnam 339–800, KoreaSearch for more papers by this authorS. Hong, S. Hong Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Electrical Engineering Department, Korea Advanced Institute ofence and Technology, 400, Kusong-Dong, Youson-Ku, Taejon 305–701, KoreaSearch for more papers by this authorK. Y. Lim, K. Y. Lim Optical Electronics Laboratory, Korea Institute ofence and Technology, Seoul Physics Department, Jeonbuk National University, Jeonjoo, Jeonbuk 560–756, KoreaSearch for more papers by this author First published: 16 May 1992 https://doi.org/10.1002/pssa.2211310149Citations: 1 Cheongryang, P.O. Box 131, Seoul 130–650, Korea. AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinked InRedditWechat Citing Literature Volume131, Issue116 May 1992Pages K77-K80 RelatedInformation

Analytical and numerical analyses of the delay time of BiCMOS structures

Analytical expressions for the transient response of BiCMOS structures have been derived. The analysis is performed on conventional structures and structures employing short-channel MOSFETs. The equations relate the delay time to key device and technology parameters. In deriving the time response, the two basic conduction regions (linear and saturation) for the MOSFET have been considered. A numerical algorithm for solving for the delay time of BiCMOS structures taking into account high-level injection effects, base resistance, doping-dependent mobilities, and bandgap narrowing is presented. A figure of merit for the speed is derived and scaling the supply voltage is considered.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Light emission from hot carriers in Si MOSFETS

Visible light emission from short-channel silicon MOSFETS biased deep into saturation is studied. A group of peaks is observed in the range of 1.3 to 2.3 eV. Devices from different manufacturers are all found to have similar luminescence features. Neither of the current models for light emission from MOSFETs, electron-hole pair recombination and bremsstrahlung emission, appears to be able to explain the observed spectra. The authors suggest that the luminescence arises from radiative transitions between conduction bands in the silicon.

Influence of series resistances and interface coupling on the transconductance of fully-depleted silicon-on-insulator MOSFETs

A model is proposed to describe the variation of the transaconductance in fully-depleted silicon on insulator MOSFETs as a function of the front/back gate biases, channel length and series resistances. The influence of series resistances on the static characteristics of short-channel transistors depends on the region of operation, via the front and back gate voltages, and is a maximum when both interfaces are inverted. Simple analytical expressions explain the gradual deformation of the transconductance curve and the lowering of the transconductance peak with increasing series resistances. The model is experimentally verified by associating external resistors to the transistor. It is shown that a major consequence of X-ray irradiations in short-channel SIMOX MOSFETs is the trapping of positive charges in the buried oxide, which causes activation of interface coupling effects and enhanced influence of series resistances.

Simple analytical model for short-channel MOS devices

A simple analytical model derived from a quasi-two-dimensional analysis with a nonvanishing E-field derivative at the pinchoff point and a continuous output conductance at the transition point for short-channel MOSFETs is presented. This model also covers mobility reduction, carrier velocity saturation, body, channel-length modulation, source-drain series resistance and short-channel effects for an accurate determination of the pinchoff point location without internal numerical iterations as compared to other models. This model can be used to describe the channel-length modulation effects more accurately in circuit simulation with short-channel MOSFETs.

Coupled Monte Carlo-energy transport simulation with quasi-three-dimensional temperature analysis for SOI MOSFET

The authors evaluate a temperature-rise effect in short-channel SOI MOSFET using a device simulator that employs a quasi-3-D temperature analysis together with 2-D coupled Monte-Carlo-energy-transport analysis. It is shown that one can accurately simulate the drain current reduction and the negative output resistance in the saturation region due to the temperature rise in the channel. It is found that the temperature rise is significantly influenced by the layout design rule such as the wiring width, the contact hole size, and the gate-to-contact hole separation. Furthermore, it is revealed that the maximum electron temperature is reduced and consequently the drain breakdown voltage is increased due to the decreased number of hot carriers with higher energy when the temperature rise is taken into account.

Dual-gate operation and volume inversion in n-channel SOI MOSFET's

The effects of volume inversion in thin-film short-channel SOI MOSFETs and the efficacy of dual-gate operation in enhancing their device performance have been analyzed using two-dimensional device simulations and one-dimensional analytical computations. The analyses have been restricted to the strong inversion regime, which is the practically useful region of operation of the SOI MOSFETs. In this region, the analyses suggest that when compared at constant V/sub G/-V/sub T/ values, the dual-channel volume inverted devices do not offer significant current-enhancement advantage, other than that expected from the second channel, over the conventional single-channel devices for silicon thicknesses in the 0.1- mu m range.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>