Short-channel MOSFETs Research Articles

Investigation of anomalous leakage current in mesa-isolated SOI MOSFETs

The mechanism of an anomalous leakage current in mesa-isolated SOI NMOSFETs in the short-channel region was analyzed. The enhanced diffusion of the source-drain impurities was observed in the mesa edge region by Energy Dispersive X-ray Spectroscopy (EDX) analysis. Moreover, using high-resolution TEM observation, it was found that there were no crystalline defects in the edge region. The frequency of leakage currents in short-channel MOSFETs was higher than that of long-channel MOSFETs. The level of leakage current was not changed by the gate voltage and back gate voltage, and the activation energy of the leakage current was almost 0 eV. According to these results, it is concluded that the origin of the anomalous leakage current is the enhanced diffusion of source-drain impurities.

An analytical model for anomalous threshold voltage behavior of short channel MOSFETs

An analytical model for anomalous threshold voltage behavior of short channel MOSFETs

Elementary scattering theory of the Si MOSFET

A simple one-flux scattering theory of the silicon MOSFET is introduced. Current-voltage (I-V) characteristics are expressed in terms of scattering parameters rather than a mobility. For long-channel transistors, the results reduce to conventional drift-diffusion theory, but they also apply to devices in which the channel length is comparable to or even shorter than the mean-free-path. The results indicate that for very short channels the transconductance is limited by carrier injection from the source. The theory also indicates that evaluation of the drain current in short-channel MOSFETs is a near-equilibrium transport problem, even though the channel electric field is large in magnitude and varies rapidly in space.

Spectroscopic photon emission measurements of n-channel MOSFETs biased into snapback breakdown using a continuous-pulsing transmission line technique

As device dimensions decrease without a proportional reduction in the supply voltage, short-channel MOSFETs may be operated at voltages close to drain-to-source breakdown. The single-pulse transmission line technique has been used previously to study devices under electrostatic discharge (ESD) as it allows the suppression of unwanted reflections. In this paper, a modified continuous-pulsing transmission line technique is combined with a spectroscopic photon emission microscope set-up to investigate photon emissions from short-channel MOSFETs biased into snapback and second breakdown. This new technique enables the photon emission spectra from a grounded-gate nMOSFET biased into snapback to be studied, with only minimal degradation to the device under test. Photon emission spectra of the grounded-gate nMOSFET biased into the snapback region showed that the spectra are a combination of the spectra for a forward-biased and reverse-biased p-n junction. A very weak emission at a wavelength of 375 nm (3.3 eV) was also detected, and this was suspected to be due to the injection of hot electrons into the gate oxide. By fitting the photon emission spectra obtained to the electron temperature model, the carrier temperature of an nMOSFET biased into snapback was also obtained.

Modeling effects of electron-velocity overshoot in a MOSFET

A simple analytical expression to account for electron-velocity overshoot effects on the performance of very short-channel MOSFETs has been obtained. This new model can be easily included in circuit simulators of systems with a huge number of components. The influence of temperature and low-field mobility on the increase of MOSFET transconductance produced by electron-velocity overshoot as channel lengths are reduced can be easily taken into account in our model. The accuracy of this model has been verified by reproducing experimental and simulated data reported by other authors.

Drain and source resistances of short-channel LDD MOSFETs

Drain and source resistances of short-channel LDD MOSFETs

The dependence of the electron mobility on the longitudinal electric field in MOSFETs

The dependence of the electron mobility on the longitudinal electric field in MOSFETs has been studied in detail. To do so, a Monte Carlo simulation of the electron dynamics in the channel, coupled with a solution of the two-dimensional Poisson equation including inversion-layer quantization and drift-diffusion equations, has been developed. A simplified description of the silicon band structure in the effective-mass approximation including non-parabolicity has been considered. Different-channel-length MOSFETs and different biases have been taken into account. It has been shown that in order to accurately describe electron-mobility behaviour in short-channel MOSFETs it is necessary to take into account the electron-velocity overshoot. An analytical expression, easy to include in device simulators, is provided to account for the dependence of the electron mobility on the high values of the longitudinal electric field and of its gradient found in state-of-the-art MOSFETs.

Identification of the Microscopic Structure of New Hot Carrier Damage Centers in Short Channel Mosfets

ABSTRACTWe show, for the first time, that E'like centers can be generated in hot hole stressing of short channel metal oxide silicon field effect transistors (MOSFETs). Prior to this study only Pb centers had been directly linked to this stressing phenomenon.

Study of the effects of a stepped doping profile in short-channel MOSFETs

The performance of a stepped doping profile for improving the short-channel behavior of a submicrometer MOSFET has been analyzed in detail by using a quasi-two-dimensional (quasi-2-D) MOSFET simulator including inversion-layer quantization coupled with a one-electron Monte Carlo simulation. Several second-order effects, such as mobility degradation both by bulk-impurity and interface traps, carrier-velocity saturation, and channel-length modulation, have been included in the simulator. Very good agreement between experimental and simulated results is obtained for short-channel transistors. It has been shown that including a low-doped zone of convenient thickness next to the interface over a high doping substrate improves both the electron mobility and the threshold voltage of the device, while avoiding short-channel effects. The use of simulation has allowed us to study certain kinds of devices without needing to make them.

A new analytical method of solving 2D Poisson's equation in MOS devices applied to threshold voltage and subthreshold modeling

In this paper we present a new theoretical approach in MOS modeling to derive analytical, physics-based model equations for the geometry and voltage dependence of threshold voltage and for the subthreshold behavior of short-channel MOSFETs. Our approach uses conformal mapping techniques to analytically solve the two-dimensional Poisson equation, whereby inhomogeneous substrate doping is taken into account. The presented model consists of analytical equations in closed form and uses only physically meaningful parameters. Therefore, the results are not only useful in circuit simulators but also in calculations of scaling behavior, where planned processes can be investigated. Comparison with numerical device simulation results and measurements confirm the high accuracy of the presented model.

Modeling of saturation transconductance for short-channel MOSFETs

By considering several secondary effects including the channel length modulation, mobility degradation, drain induced barrier lowering, and threshold voltage variation, an accurate saturation transconductance model for short-channel MOSFETs is developed. The calculated values of saturation transconductance agree well with the BSIM3 simulation results and the experimental results for devices with effective channel length in the range of 0.44-10 μm. This model has the advantages of less number of model parameters and can be used to analyze the small signal performance of analog circuits.

Analysis of the validity of methods for extracting the effective channel length of short-channel LDD MOSFETs

Analysis of the validity of methods for extracting the effective channel length of short-channel LDD MOSFETs

Accurate simultaneous switching noise estimation including velocity-saturation effects

Simultaneous switching noise (SSN) on power supply lines is caused by the large switching transient currents flowing through parasitic inductances at the chip-package-pin interface. A new expression to estimate SSN in CMOS circuits that includes the velocity saturation effects seen in the short-channel MOSFETs is derived. SPICE Level 3 simulation results show that the formula predicts the SSN more accurately as compared to existing approaches for submicron processes even at reduced supply voltages.

Characterization of nonlinear substrate resistance in short-channel MOSFETs

The substrate current conduction in the short-channel MOSFET is described as a virtual JFET coupled with the intrinsic MOSFET. A method to extract the I-V characteristics of the substrate-JFET from I-V measurements on the MOSFET, and pertinent results for a few varied MOSFET structures are presented. The JFET model and characteristics appear valid for the structures investigated, and reveal the fact that modulation by the depletion regions of the source and drain junctions is a major factor in the nonlinearity of the substrate resistance of actual MOSFETs. The nonlinearity of the substrate resistance needs to be considered for an accurate description of the drain-voltage induced limitation of a standard MOSFET. Also, the pinch-off of the substrate-JFET offers a physical explanation to the "early" turn on, a type of drain-voltage limitation present in the short-channel MOSFET when the depletion regions of the source and drain merge in the depth of the channel.

Low-Temperature Modelling of Electron-Velocity-Overshoot Effects on 70-250 nm Gate-Length MOSFETs

Modelling of the increase of MOSFET transconductance produced by electron-velocity overshoot as channel lengths are reduced has been performed at low temperature. The results obtained have been compared to room-temperature ones. To accomplish this, the charge-control model has been used to obtain a simple analytical expression to account for electron-velocity overshoot effects on the performance of very short channel MOSFETs. This model can be easily included in circuit simulators of systems with a huge number of components. Experimental verification of the accuracy of this model is provided. The improvement of MOSFET transconductance due to electron-velocity overshoot is found to be greater at low temperature than at room temperature.

Comparisons and extension of recent surface potential models for fully depleted short-channel SOI MOSFET's

Recent surface potential models for fully depleted short-channel SOI MOSFET's are compared. The parabolic potential approach is clarified to be a special case of the quasi-2-D approach. An extended quasi-2-D model is also derived.

Thermal noise modeling for short-channel MOSFETs

An analytical formulation of the thermal noise in short-channel MOSFETs, working in the saturation region, is presented. For the noise calculation, we took into account effects like the field dependent noise temperature and mobility, the device geometry and the channel length modulation, the back gate effect and the velocity saturation. The derived data from the model are in good agreement with reported thermal noise measurements, regarding the noise bias dependence, for transistors with channel lengths shorter than 1 /spl mu/m. Since the present thermal noise models of MOS transistors are valid for channel lengths well above 1 /spl mu/m, the proposed model can be easily incorporated in circuit simulators like SPICE, providing an extension to the analytical thermal noise modeling suitable for submicron MOSFETs.

Effects of source/drain implants on short-channel MOSFET I-V and C-V characteristics

The effects of source/drain implants on n-channel MOSFET I-V and C-V characteristics are measured and compared for the lightly doped drain (LDD) and the large-angle-tilt implanted drain (LATID) devices. We show that despite substantial improvement in hot-carrier reliability for LATID devices, the LATID design might have a limited range of application for short-channel MOSFETs. This is because as a result of enhanced V/sub TH/ roll-off and increased overlap capacitance for the LATID devices compared to LDD devices, the device/circuit performance degrades. The degradation of performance becomes more pronounced as device length is reduced. These results are confirmed by both experimental data and 2-dimensional numerical simulations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Modeling and simulation of homogeneous degradation for N-channel MOSFETS

In this work, the effects of the degradation generated by homogeneous hot-electron injection in a one-dimensional model of current-voltage characteristics for short-channel MOSFETs are introduced. A distributed charge model, implemented in the SABER simulator is used. Simulation results obtained for n-MOS transistors demonstrate good agreement with the experimental data for interface state density inferior to 3 × 10 11 cm −2 eV −1. The samples are degraded by homogeneous electron photoinjection and the interface trap density is performed by the pumping charge method.

Two-dimensional numerical analysis for extracting the effective channel length of short-channel MOSFETs

Device simulations are carried out to study the physical mechanisms underlying the effective channel length of MOSFETs. Furthermore, the adequacy of widely used methods for extracting such a parameter is examined using different free-carrier mobility models implemented in the device simulator. It is shown that the conventional definition for the effective channel length using the locations of source/drain junctions is questionable. Based on the simulation results, a more consistent and accurate definition for determining the effective channel length is also proposed.